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Design of 3D-IC for butterfly NOC based 64 PE-multicore: Analysis and design space exploration

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Abstract

3D Conception is an efficient solution to deal with the global wiring delay which is overcoming the gates delay in nanometres CMOS technology. We present in this paper, the implementation of a butterfly NOC based 64 PE multicore using 3D-IC Tezzaron technology. In order to design a 3D NOC, we present different partionning configurations. Thanks to the 3D implementation with 2 tiers, we reduced the area of the chip to the half and we reduced the long interconnect delay.

Original languageEnglish
Title of host publication2011 IEEE International 3D Systems Integration Conference, 3DIC 2011
DOIs
Publication statusPublished - 1 Dec 2011
Event2011 IEEE International 3D Systems Integration Conference, 3DIC 2011 - Osaka, Japan
Duration: 31 Jan 20122 Feb 2012

Publication series

Name2011 IEEE International 3D Systems Integration Conference, 3DIC 2011

Conference

Conference2011 IEEE International 3D Systems Integration Conference, 3DIC 2011
Country/TerritoryJapan
CityOsaka
Period31/01/122/02/12

Keywords

  • 3D IC
  • 3D NoC
  • MPSoC
  • Tezzaron
  • butterfly

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