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Design of embedded MRAM macros for memory-in-logic applications

  • Sumanta Chaudhuri
  • , Weisheng Zhao
  • , Jacques Olivier Klein
  • , Claude Chappert
  • , Pascale Mazoyer
  • Université Paris-Saclay
  • Centre national de la recherche scientifique
  • STMicroelectronics SA, France

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

In this article we present a design method for integrating non-volatile MRAM memory cells into standard CMOS design. The emphasis is on standard cell based flow for general purpose logic and automatic generation or MRAM macros suitable for the applications. We present a design space exploration for this purpose and transient simulation results of the hybrid MTJ/CMOS designs. We continue the article with examples of automatic macro generation, integration layout and a prototype in 130nm CMOS which is designed to test a large subset of this design space. In conclusion we show that a high 3D integration density with reasonable speed can be achieved with automatic flow by sharing the reading/writing circuitry among a number of MTJs.

Original languageEnglish
Title of host publicationGLSVLSI'10 - Proceedings of the Great Lakes Symposium on VLSI 2010
Pages155-158
Number of pages4
DOIs
Publication statusPublished - 16 Jul 2010
Event20th Great Lakes Symposium on VLSI, GLSVLSI 2010 - Providence, RI, United States
Duration: 16 May 201018 May 2010

Publication series

NameProceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Conference

Conference20th Great Lakes Symposium on VLSI, GLSVLSI 2010
Country/TerritoryUnited States
CityProvidence, RI
Period16/05/1018/05/10

Keywords

  • architecture
  • embedded
  • low power
  • mram
  • non-volatile
  • system on chip (soc)
  • thermally assisted switching (tas)

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