TY - GEN
T1 - Design, synthesis and application of a novel approximate adder
AU - Ban, Tian
AU - Wang, Baokun
AU - Naviner, Lirida
N1 - Publisher Copyright:
© 2018 IEEE
PY - 2018/7/2
Y1 - 2018/7/2
N2 - Approximate computing is a new design paradigm in VLSI design and test. It can improve the performance of error-tolerant applications at the expense of slight loss in computational accuracy. In this paper, we propose a novel approximate adder with a hybrid structure (HYB-adder) which produces results of different precision. The proposed adder is synthesized by utilizing 28nm FD-SOI (fully-depleted silicon-on-insulator) technology. The proposed HYB-adder outperforms existing approximate adder designs regarding mean error distance with comparable area, delay and power consumption. The efficiency is also validated by its application in DCT/IDCT procedures.
AB - Approximate computing is a new design paradigm in VLSI design and test. It can improve the performance of error-tolerant applications at the expense of slight loss in computational accuracy. In this paper, we propose a novel approximate adder with a hybrid structure (HYB-adder) which produces results of different precision. The proposed adder is synthesized by utilizing 28nm FD-SOI (fully-depleted silicon-on-insulator) technology. The proposed HYB-adder outperforms existing approximate adder designs regarding mean error distance with comparable area, delay and power consumption. The efficiency is also validated by its application in DCT/IDCT procedures.
U2 - 10.1109/MWSCAS.2018.8624023
DO - 10.1109/MWSCAS.2018.8624023
M3 - Conference contribution
AN - SCOPUS:85062208742
T3 - Midwest Symposium on Circuits and Systems
SP - 488
EP - 491
BT - 2018 IEEE 61st International Midwest Symposium on Circuits and Systems, MWSCAS 2018
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 61st IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2018
Y2 - 5 August 2018 through 8 August 2018
ER -