TY - GEN
T1 - DPL on stratix II FPGA
T2 - 2009 International Conference on ReConFigurable Computing and FPGAs, ReConFig'09
AU - Sauvage, Laurent
AU - Nassar, Maxime
AU - Guilley, Sylvain
AU - Flament, Florent
AU - Danger, Jean Luc
AU - Mathieu, Yves
PY - 2009/12/1
Y1 - 2009/12/1
N2 - FPGA design of side channel analysis countermeasure using unmasked dual-rail with precharge logic appears to be a great challenge. Indeed, the robustness of such a solution relies on careful differential placement and routing, whereas both FPGA layout and FPGA EDA tools are not developed for such purposes. However, assessing the security level which can be achieved with them is an important issue, as it is directly related to the suitability to use commercial FPGA instead of proprietary custom FPGA for this kind of protection. In this article, we experimentally prove that differential placement and routing of an FPGA implementation can be done with a granularity fine enough to improve the security gain. However, the gain is lower than for ASICs. We expect that an in-depth analysis of routing resources power consumption could help bridge the gap.
AB - FPGA design of side channel analysis countermeasure using unmasked dual-rail with precharge logic appears to be a great challenge. Indeed, the robustness of such a solution relies on careful differential placement and routing, whereas both FPGA layout and FPGA EDA tools are not developed for such purposes. However, assessing the security level which can be achieved with them is an important issue, as it is directly related to the suitability to use commercial FPGA instead of proprietary custom FPGA for this kind of protection. In this article, we experimentally prove that differential placement and routing of an FPGA implementation can be done with a granularity fine enough to improve the security gain. However, the gain is lower than for ASICs. We expect that an in-depth analysis of routing resources power consumption could help bridge the gap.
KW - Commercial Off-The-Shelf (COTS)
KW - Differential Power Analysis (DPA)
KW - Dual-rail with Precharge Logic (DPL)
KW - Field Programmable Gates Array (FPGA)
KW - Side-Channel Analysis (SCA)
KW - Wave Dynamic Differential Logic (WDDL)
U2 - 10.1109/ReConFig.2009.58
DO - 10.1109/ReConFig.2009.58
M3 - Conference contribution
AN - SCOPUS:77950499772
SN - 9780769539171
T3 - ReConFig'09 - 2009 International Conference on ReConFigurable Computing and FPGAs
SP - 243
EP - 248
BT - ReConFig'09 - 2009 International Conference on ReConFigurable Computing and FPGAs
Y2 - 9 December 2009 through 11 December 2009
ER -