Dynamic power management on LDPC decoders

Erick Amador; Raymond Knopp; Vincent Rezard; Renaud Pacalet

doi:10.1109/isvlsi.2010.70

Dynamic power management on LDPC decoders

Erick Amador, Raymond Knopp, Vincent Rezard, Renaud Pacalet

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

This paper presents a dynamic power management strategy for the iterative decoding of low-density parity-check (LDPC) codes. We propose an online algorithm for adjusting the operation of a power manageable decoder. Decision making is based upon the monitoring of a convergence metric independent from the message computation kernel. Furthermore we analyze the feasibility of a VLSI Implementation for such algorithm. Up to 54% savings in energy were achieved with a relatively low loss on error-correcting performance.

Original language	English
Title of host publication	Proceedings - IEEE Annual Symposium on VLSI, ISVLSI 2010
Publisher	IEEE Computer Society
Pages	416-421
Number of pages	6
ISBN (Print)	9780769540764
DOIs	https://doi.org/10.1109/isvlsi.2010.70
Publication status	Published - 1 Jan 2010

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Name	Proceedings - IEEE Annual Symposium on VLSI, ISVLSI 2010

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10.1109/isvlsi.2010.70

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title = "Dynamic power management on LDPC decoders",

abstract = "This paper presents a dynamic power management strategy for the iterative decoding of low-density parity-check (LDPC) codes. We propose an online algorithm for adjusting the operation of a power manageable decoder. Decision making is based upon the monitoring of a convergence metric independent from the message computation kernel. Furthermore we analyze the feasibility of a VLSI Implementation for such algorithm. Up to 54\% savings in energy were achieved with a relatively low loss on error-correcting performance.",

author = "Erick Amador and Raymond Knopp and Vincent Rezard and Renaud Pacalet",

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N2 - This paper presents a dynamic power management strategy for the iterative decoding of low-density parity-check (LDPC) codes. We propose an online algorithm for adjusting the operation of a power manageable decoder. Decision making is based upon the monitoring of a convergence metric independent from the message computation kernel. Furthermore we analyze the feasibility of a VLSI Implementation for such algorithm. Up to 54% savings in energy were achieved with a relatively low loss on error-correcting performance.

AB - This paper presents a dynamic power management strategy for the iterative decoding of low-density parity-check (LDPC) codes. We propose an online algorithm for adjusting the operation of a power manageable decoder. Decision making is based upon the monitoring of a convergence metric independent from the message computation kernel. Furthermore we analyze the feasibility of a VLSI Implementation for such algorithm. Up to 54% savings in energy were achieved with a relatively low loss on error-correcting performance.

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DO - 10.1109/isvlsi.2010.70

M3 - Conference contribution

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BT - Proceedings - IEEE Annual Symposium on VLSI, ISVLSI 2010

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Dynamic power management on LDPC decoders

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