Effective compiler generation by architecture description

Stefan Farfeleder, Andreas Krall, Edwin Steiner, Florian Brandner

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Embedded systems have an extremely short time to market and therefore require easily retargetable compilers. Architecture description languages (ADLs) provide a single concise architecture specification for the generation of hardware, instruction set simulators and compilers. In this article, we present an ADL for compiler generation. From a specification, we can derive an optimized tree pattern matching instruction selector, a register allocator and an instruction scheduler. Compared to a hand-crafted back end, the generated compiler produces smaller and faster code. The ADL is rich enough that other tools, such as assemblers, linkers, simulators and documentation, can all be obtained from a single specification.

Original languageEnglish
Title of host publicationLCTES 2006 - Proceedings of the 2006 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems
PublisherAssociation for Computing Machinery
Pages145-152
Number of pages8
ISBN (Print)159593362X, 9781595933621
DOIs
Publication statusPublished - 1 Jan 2006
Externally publishedYes
EventLCTES 2006 - 2006 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems - Ottawa, ON, Canada
Duration: 14 Jun 200616 Jun 2006

Publication series

NameProceedings of the ACM SIGPLAN Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES)
Volume2006

Conference

ConferenceLCTES 2006 - 2006 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems
Country/TerritoryCanada
CityOttawa, ON
Period14/06/0616/06/06

Keywords

  • Architecture description language
  • Code generation
  • Compiler generation

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