Efficient computation of combinational circuits reliability based on probabilistic transfer matrix

Lirida Naviner; Kaikai Liu; Hao Cai; Jean François Naviner

doi:10.1109/ICICDT.2014.6838588

Efficient computation of combinational circuits reliability based on probabilistic transfer matrix

Lirida Naviner, Kaikai Liu, Hao Cai, Jean François Naviner

Institut Mines-Télécom

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

The rapid dimension scaling of CMOS has introduced many new challenges. One of them is to design reliable circuits with unreliable devices. Probabilistic transfer matrix (PTM) has proven to be an accurate method to evaluate the reliability of a combinational circuit. However, it requires a lot of time consumption and memory usage, which makes it unsuitable for large circuits. In this paper, we propose optimizations on PTM calculation that allow to obtain accurate reliability while reducing computational and memory needs. Some benchmark circuits have been tested to verify the efficiency of the proposed method by comparing its time consumption and memory usage with the traditional PTM implementation.

Original language	English
Title of host publication	ICICDT 2014 - IEEE International Conference on Integrated Circuit Design and Technology
Publisher	IEEE Computer Society
ISBN (Print)	9781479921539
DOIs	https://doi.org/10.1109/ICICDT.2014.6838588
Publication status	Published - 1 Jan 2014
Externally published	Yes
Event	2014 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2014 - Austin, TX, United States Duration: 28 May 2014 → 30 May 2014

Publication series

Name	ICICDT 2014 - IEEE International Conference on Integrated Circuit Design and Technology

Conference

Conference	2014 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2014
Country/Territory	United States
City	Austin, TX
Period	28/05/14 → 30/05/14

Access to Document

10.1109/ICICDT.2014.6838588

Cite this

Naviner, L., Liu, K., Cai, H., & Naviner, J. F. (2014). Efficient computation of combinational circuits reliability based on probabilistic transfer matrix. In ICICDT 2014 - IEEE International Conference on Integrated Circuit Design and Technology Article 6838588 (ICICDT 2014 - IEEE International Conference on Integrated Circuit Design and Technology). IEEE Computer Society. https://doi.org/10.1109/ICICDT.2014.6838588

@inproceedings{a349edfccfdc4a5b870ea8dfb7d11a41,

title = "Efficient computation of combinational circuits reliability based on probabilistic transfer matrix",

abstract = "The rapid dimension scaling of CMOS has introduced many new challenges. One of them is to design reliable circuits with unreliable devices. Probabilistic transfer matrix (PTM) has proven to be an accurate method to evaluate the reliability of a combinational circuit. However, it requires a lot of time consumption and memory usage, which makes it unsuitable for large circuits. In this paper, we propose optimizations on PTM calculation that allow to obtain accurate reliability while reducing computational and memory needs. Some benchmark circuits have been tested to verify the efficiency of the proposed method by comparing its time consumption and memory usage with the traditional PTM implementation.",

author = "Lirida Naviner and Kaikai Liu and Hao Cai and Naviner, \{Jean Fran{\c c}ois\}",

year = "2014",

month = jan,

day = "1",

doi = "10.1109/ICICDT.2014.6838588",

language = "English",

isbn = "9781479921539",

series = "ICICDT 2014 - IEEE International Conference on Integrated Circuit Design and Technology",

publisher = "IEEE Computer Society",

booktitle = "ICICDT 2014 - IEEE International Conference on Integrated Circuit Design and Technology",

note = "2014 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2014 ; Conference date: 28-05-2014 Through 30-05-2014",

}

Naviner, L, Liu, K, Cai, H & Naviner, JF 2014, Efficient computation of combinational circuits reliability based on probabilistic transfer matrix. in ICICDT 2014 - IEEE International Conference on Integrated Circuit Design and Technology., 6838588, ICICDT 2014 - IEEE International Conference on Integrated Circuit Design and Technology, IEEE Computer Society, 2014 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2014, Austin, TX, United States, 28/05/14. https://doi.org/10.1109/ICICDT.2014.6838588

Efficient computation of combinational circuits reliability based on probabilistic transfer matrix. / Naviner, Lirida; Liu, Kaikai; Cai, Hao et al.
ICICDT 2014 - IEEE International Conference on Integrated Circuit Design and Technology. IEEE Computer Society, 2014. 6838588 (ICICDT 2014 - IEEE International Conference on Integrated Circuit Design and Technology).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Efficient computation of combinational circuits reliability based on probabilistic transfer matrix

AU - Naviner, Lirida

AU - Liu, Kaikai

AU - Cai, Hao

AU - Naviner, Jean François

PY - 2014/1/1

Y1 - 2014/1/1

N2 - The rapid dimension scaling of CMOS has introduced many new challenges. One of them is to design reliable circuits with unreliable devices. Probabilistic transfer matrix (PTM) has proven to be an accurate method to evaluate the reliability of a combinational circuit. However, it requires a lot of time consumption and memory usage, which makes it unsuitable for large circuits. In this paper, we propose optimizations on PTM calculation that allow to obtain accurate reliability while reducing computational and memory needs. Some benchmark circuits have been tested to verify the efficiency of the proposed method by comparing its time consumption and memory usage with the traditional PTM implementation.

AB - The rapid dimension scaling of CMOS has introduced many new challenges. One of them is to design reliable circuits with unreliable devices. Probabilistic transfer matrix (PTM) has proven to be an accurate method to evaluate the reliability of a combinational circuit. However, it requires a lot of time consumption and memory usage, which makes it unsuitable for large circuits. In this paper, we propose optimizations on PTM calculation that allow to obtain accurate reliability while reducing computational and memory needs. Some benchmark circuits have been tested to verify the efficiency of the proposed method by comparing its time consumption and memory usage with the traditional PTM implementation.

U2 - 10.1109/ICICDT.2014.6838588

DO - 10.1109/ICICDT.2014.6838588

M3 - Conference contribution

AN - SCOPUS:84904205360

SN - 9781479921539

T3 - ICICDT 2014 - IEEE International Conference on Integrated Circuit Design and Technology

BT - ICICDT 2014 - IEEE International Conference on Integrated Circuit Design and Technology

PB - IEEE Computer Society

T2 - 2014 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2014

Y2 - 28 May 2014 through 30 May 2014

ER -

Naviner L, Liu K, Cai H, Naviner JF. Efficient computation of combinational circuits reliability based on probabilistic transfer matrix. In ICICDT 2014 - IEEE International Conference on Integrated Circuit Design and Technology. IEEE Computer Society. 2014. 6838588. (ICICDT 2014 - IEEE International Conference on Integrated Circuit Design and Technology). doi: 10.1109/ICICDT.2014.6838588

Efficient computation of combinational circuits reliability based on probabilistic transfer matrix

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