Efficient computation of logic circuits reliability based on probabilistic transfer matrix

Lirida A.B. Naviner; Maí C.R. De Vasconcelos; Denis T. Franco; Jean François Naviner

doi:10.1109/DTIS.2008.4540217

Efficient computation of logic circuits reliability based on probabilistic transfer matrix

Lirida A.B. Naviner
, Maí C.R. De Vasconcelos
, Denis T. Franco
, Jean François Naviner

CNRS LTCI

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

The development of fault tolerance techniques to enhance systems dependability is becoming an unavoidable task as IC industry enters in the nanoscale era. However, before consider the fault tolerant design, an accurate method of reliability evaluation is necessary. The knowledge of the natural error masking capabilities of a given circuit will be essential to handle design tradeoffs in the conception stage. This paper is intended to deal with improvements in the reliability computation of logic circuits using the Probabilistic Transfer Matrix (PTM) approach. We propose an algorithm that reduces memory requirements and can improve run-time performances in the most significant stage of the PTM algorithm, keeping the same accurate reliability analysis.

Original language	English
Title of host publication	International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS'08
DOIs	https://doi.org/10.1109/DTIS.2008.4540217
Publication status	Published - 10 Sept 2008
Externally published	Yes
Event	nternational Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS'08 - Tozeur, Tunisia Duration: 25 Mar 2008 → 27 Mar 2008

Publication series

Name	International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS'08

Conference

Conference	nternational Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS'08
Country/Territory	Tunisia
City	Tozeur
Period	25/03/08 → 27/03/08

Access to Document

10.1109/DTIS.2008.4540217

Cite this

Naviner, L. A. B., De Vasconcelos, M. C. R., Franco, D. T., & Naviner, J. F. (2008). Efficient computation of logic circuits reliability based on probabilistic transfer matrix. In International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS'08 Article 4540217 (International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS'08). https://doi.org/10.1109/DTIS.2008.4540217

Naviner, Lirida A.B. ; De Vasconcelos, Maí C.R. ; Franco, Denis T. et al. / Efficient computation of logic circuits reliability based on probabilistic transfer matrix. International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS'08. 2008. (International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS'08).

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title = "Efficient computation of logic circuits reliability based on probabilistic transfer matrix",

abstract = "The development of fault tolerance techniques to enhance systems dependability is becoming an unavoidable task as IC industry enters in the nanoscale era. However, before consider the fault tolerant design, an accurate method of reliability evaluation is necessary. The knowledge of the natural error masking capabilities of a given circuit will be essential to handle design tradeoffs in the conception stage. This paper is intended to deal with improvements in the reliability computation of logic circuits using the Probabilistic Transfer Matrix (PTM) approach. We propose an algorithm that reduces memory requirements and can improve run-time performances in the most significant stage of the PTM algorithm, keeping the same accurate reliability analysis.",

author = "Naviner, \{Lirida A.B.\} and \{De Vasconcelos\}, \{Ma{\'i} C.R.\} and Franco, \{Denis T.\} and Naviner, \{Jean Fran{\c c}ois\}",

year = "2008",

month = sep,

day = "10",

doi = "10.1109/DTIS.2008.4540217",

language = "English",

isbn = "9781424415779",

series = "International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS'08",

booktitle = "International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS'08",

note = "nternational Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS'08 ; Conference date: 25-03-2008 Through 27-03-2008",

}

Naviner, LAB, De Vasconcelos, MCR, Franco, DT & Naviner, JF 2008, Efficient computation of logic circuits reliability based on probabilistic transfer matrix. in International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS'08., 4540217, International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS'08, nternational Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS'08, Tozeur, Tunisia, 25/03/08. https://doi.org/10.1109/DTIS.2008.4540217

Efficient computation of logic circuits reliability based on probabilistic transfer matrix. / Naviner, Lirida A.B.; De Vasconcelos, Maí C.R.; Franco, Denis T. et al.
International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS'08. 2008. 4540217 (International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS'08).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Efficient computation of logic circuits reliability based on probabilistic transfer matrix

AU - Naviner, Lirida A.B.

AU - De Vasconcelos, Maí C.R.

AU - Franco, Denis T.

AU - Naviner, Jean François

PY - 2008/9/10

Y1 - 2008/9/10

N2 - The development of fault tolerance techniques to enhance systems dependability is becoming an unavoidable task as IC industry enters in the nanoscale era. However, before consider the fault tolerant design, an accurate method of reliability evaluation is necessary. The knowledge of the natural error masking capabilities of a given circuit will be essential to handle design tradeoffs in the conception stage. This paper is intended to deal with improvements in the reliability computation of logic circuits using the Probabilistic Transfer Matrix (PTM) approach. We propose an algorithm that reduces memory requirements and can improve run-time performances in the most significant stage of the PTM algorithm, keeping the same accurate reliability analysis.

AB - The development of fault tolerance techniques to enhance systems dependability is becoming an unavoidable task as IC industry enters in the nanoscale era. However, before consider the fault tolerant design, an accurate method of reliability evaluation is necessary. The knowledge of the natural error masking capabilities of a given circuit will be essential to handle design tradeoffs in the conception stage. This paper is intended to deal with improvements in the reliability computation of logic circuits using the Probabilistic Transfer Matrix (PTM) approach. We propose an algorithm that reduces memory requirements and can improve run-time performances in the most significant stage of the PTM algorithm, keeping the same accurate reliability analysis.

UR - https://www.scopus.com/pages/publications/51049121623

U2 - 10.1109/DTIS.2008.4540217

DO - 10.1109/DTIS.2008.4540217

M3 - Conference contribution

AN - SCOPUS:51049121623

SN - 9781424415779

T3 - International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS'08

BT - International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS'08

T2 - nternational Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS'08

Y2 - 25 March 2008 through 27 March 2008

ER -

Naviner LAB, De Vasconcelos MCR, Franco DT, Naviner JF. Efficient computation of logic circuits reliability based on probabilistic transfer matrix. In International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS'08. 2008. 4540217. (International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS'08). doi: 10.1109/DTIS.2008.4540217

Efficient computation of logic circuits reliability based on probabilistic transfer matrix

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