Efficient dual-rail implementations in FPGA using block RAMs

Dual-rail precharge logic (DPL) are hardware countermeasures deployed to protect cryptographic coprocessors. However, their implementation on FPGA has been an issue of concern mainly due to imbalanced routing and early propagation effect. We analyzed the causes due to which DPL implementation on FPGA usually fails and previously proposed solutions. Many articles report that early propagation effect can be countered by synchronization mechanisms but routing imbalance is still a problem. In this article, we propose fan out reduction as a solution to counter routing imbalance. We found that the nets which have high fan out can be routed asymmetrically and therefore leak in the side channel. Another cause of imbalance in routing is long timing paths. Reduction of fan out and no. of gates in timing path can be achieved by using memories for implementing majority of cryptographic part. We use balanced-cell based dual rail logic (BCDL) which is a glitch-free DPL capable of using memories efficiently. Next, we present a source-level coding style to efficiently implement BCDL using block RAMs in FPGAs. This is followed by side channel analysis on Stratix II FPGA and results show that with fan out reduction we need 14 times more traces to find the key.