TY - GEN
T1 - Efficient modeling and floorplanning of embedded-FPGA fabric
AU - Chaudhuri, Sumanta
AU - Danger, Jean Luc
AU - Guilley, Sylvain
PY - 2007/12/1
Y1 - 2007/12/1
N2 - In this paper we present an automatic design flow for generating customized embedded FPGA (eFPGA) fabric and a domain specific SOC+eFPGA architecture. This design flow encompasses both the eFPGA user and automatic layout generator perspectives. We discuss generic FPGA modeling based on VPR tool, simulation and high-level models of reconfigurable components, and we present an innovative floor-planing for island style FPGAs using rectilinear macros. Several system integration issues are highlighted. Layout of a real life SOC with an embedded RTR FPGA for cryptographic applications, designed with this flow, is also presented.
AB - In this paper we present an automatic design flow for generating customized embedded FPGA (eFPGA) fabric and a domain specific SOC+eFPGA architecture. This design flow encompasses both the eFPGA user and automatic layout generator perspectives. We discuss generic FPGA modeling based on VPR tool, simulation and high-level models of reconfigurable components, and we present an innovative floor-planing for island style FPGAs using rectilinear macros. Several system integration issues are highlighted. Layout of a real life SOC with an embedded RTR FPGA for cryptographic applications, designed with this flow, is also presented.
U2 - 10.1109/FPL.2007.4380741
DO - 10.1109/FPL.2007.4380741
M3 - Conference contribution
AN - SCOPUS:48149086232
SN - 1424410606
SN - 9781424410606
T3 - Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL
SP - 665
EP - 669
BT - Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL
T2 - 2007 International Conference on Field Programmable Logic and Applications, FPL
Y2 - 27 August 2007 through 29 August 2007
ER -