@inproceedings{3b00817cf1814683a435e06e153370b9,
title = "Efficient tiling patterns for reconfigurable gate arrays",
abstract = "In this paper we present a few potentially efficient tiling patterns for gate-array realizations. We start with a brief recapitulation of tiling patterns, and fundamental limits of placement/routing in a two-dimensional plane. We state the first principles (i.e. Rent's Rule, Donath's result, equivalence of wire flux and wire length) and we proceed to define a method to mathematically evaluate tiling patterns based on these principles. With this method we analyze a few regular tiling patterns and present a layout scheme for hexagonal and octagonal FPGAs. We briefly discuss the hierarchical gate array and we conclude with emphasis on the necessity of evolution of tiling patterns with the technology.",
keywords = "FPGA, Hexagonal, Octagonal, Tiling",
author = "Sumanta Chaudhuri and Sylvain Guilley and Philippe Hoogvorst and Danger, \{Jean Luc\}",
year = "2008",
month = may,
day = "16",
doi = "10.1145/1353610.1353613",
language = "English",
isbn = "9781595939180",
series = "International Workshop on System Level Interconnect Prediction, SLIP",
pages = "19--26",
booktitle = "SLIP'08 - Proceedings of the 2008 ACM International Workshop on System Level Interconnect Prediction",
note = "10th ACM International Workshop on System-Level Interconnect Prediction, SLIP 2008 ; Conference date: 05-04-2008 Through 06-04-2008",
}