TY - GEN
T1 - EM Fault Injection-Induced Clock Glitches
T2 - 30th IEEE International Symposium on On-line Testing and Robust System Design, IOLTS 2024
AU - Nabhan, Roukoz
AU - Dutertre, Jean Max
AU - Rigaud, Jean Baptiste
AU - Danger, Jean Luc
AU - Sauvage, Laurent
N1 - Publisher Copyright:
© 2024 IEEE.
PY - 2024/1/1
Y1 - 2024/1/1
N2 - This paper introduces a novel sensor that is capable of detecting faults injected by electromagnetic disturbances. The sensor has been designed from an understanding of the physical mechanisms of ElectroMagnetic Fault Injection (EMFI). A recent study has identified an EMFI mechanism based on the timing violation fault model, which highlights the coexistence of two distinct mechanisms: electromagnetic disturbances that are coupled to the target's power distribution network, which can cause timing faults by extending the propagation time of logic gates beyond the clock period, and disturbances that are coupled to the target's clock distribution network, which can cause timing constraint violations due to EMFI-induced voltage glitches within the target's clock tree. Building on this work, we have investigated the mechanism of EMFI-induced clock glitches, providing useful insights for designing a new sensor. The sensor incorporates two dummy clock paths that are maintained in a frozen state within the circuit. Both paths are respectively capable of detecting both positive and negative EMFI-induced glitches along these paths. The proposed sensor offers significant advantages, including full digitization, ease of implementation, low cost in terms of silicon area, low power consumption, and a high fault detection rate. Accurate design and experimental tests were performed on an FPGA board. Validation experiments were supported by spatial and temporal sensitivity maps covering the full-frequency spectrum of the target, which confirmed the effectiveness of the sensor.
AB - This paper introduces a novel sensor that is capable of detecting faults injected by electromagnetic disturbances. The sensor has been designed from an understanding of the physical mechanisms of ElectroMagnetic Fault Injection (EMFI). A recent study has identified an EMFI mechanism based on the timing violation fault model, which highlights the coexistence of two distinct mechanisms: electromagnetic disturbances that are coupled to the target's power distribution network, which can cause timing faults by extending the propagation time of logic gates beyond the clock period, and disturbances that are coupled to the target's clock distribution network, which can cause timing constraint violations due to EMFI-induced voltage glitches within the target's clock tree. Building on this work, we have investigated the mechanism of EMFI-induced clock glitches, providing useful insights for designing a new sensor. The sensor incorporates two dummy clock paths that are maintained in a frozen state within the circuit. Both paths are respectively capable of detecting both positive and negative EMFI-induced glitches along these paths. The proposed sensor offers significant advantages, including full digitization, ease of implementation, low cost in terms of silicon area, low power consumption, and a high fault detection rate. Accurate design and experimental tests were performed on an FPGA board. Validation experiments were supported by spatial and temporal sensitivity maps covering the full-frequency spectrum of the target, which confirmed the effectiveness of the sensor.
KW - EMFI
KW - EMFI induced clock glitches
KW - digital sensor
KW - timing violations fault model
U2 - 10.1109/IOLTS60994.2024.10616074
DO - 10.1109/IOLTS60994.2024.10616074
M3 - Conference contribution
AN - SCOPUS:85201408424
T3 - Proceedings - 2024 IEEE 30th International Symposium on On-line Testing and Robust System Design, IOLTS 2024
BT - Proceedings - 2024 IEEE 30th International Symposium on On-line Testing and Robust System Design, IOLTS 2024
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 3 July 2024 through 5 July 2024
ER -