Embedded processors optimization with hardware in the loop

K. Ghali; O. Hammami

doi:10.1109/ISIE.2004.1571868

Embedded processors optimization with hardware in the loop

K. Ghali, O. Hammami

IEEE

Research output: Contribution to conference › Paper › peer-review

Abstract

The design of an embedded microprocessor for a given workload is a tremendous task by itself due to the numerous parameters involved and the ranges of their possible values. If power consumption and area are also to be considered then the problem is even more complicated and requires a suitable framework and methodology for exploring the vast multidimensional space for such a problem. In this paper we propose such a framework based onl direct execution on FPGA boards.

Original language	English
Pages	561-564
Number of pages	4
DOIs	https://doi.org/10.1109/ISIE.2004.1571868
Publication status	Published - 1 Dec 2004
Event	2004 IEEE International Symposium on Industrial Electronics, IEEE-ISlE - Duration: 4 May 2004 → 7 May 2004

Conference

Conference	2004 IEEE International Symposium on Industrial Electronics, IEEE-ISlE
Period	4/05/04 → 7/05/04

Keywords

Embedded
FPGA
Processor

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10.1109/ISIE.2004.1571868

Cite this

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title = "Embedded processors optimization with hardware in the loop",

abstract = "The design of an embedded microprocessor for a given workload is a tremendous task by itself due to the numerous parameters involved and the ranges of their possible values. If power consumption and area are also to be considered then the problem is even more complicated and requires a suitable framework and methodology for exploring the vast multidimensional space for such a problem. In this paper we propose such a framework based onl direct execution on FPGA boards.",

keywords = "Embedded, FPGA, Processor",

author = "K. Ghali and O. Hammami",

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doi = "10.1109/ISIE.2004.1571868",

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AU - Hammami, O.

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AB - The design of an embedded microprocessor for a given workload is a tremendous task by itself due to the numerous parameters involved and the ranges of their possible values. If power consumption and area are also to be considered then the problem is even more complicated and requires a suitable framework and methodology for exploring the vast multidimensional space for such a problem. In this paper we propose such a framework based onl direct execution on FPGA boards.

KW - Embedded

KW - FPGA

KW - Processor

U2 - 10.1109/ISIE.2004.1571868

DO - 10.1109/ISIE.2004.1571868

M3 - Paper

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EP - 564

T2 - 2004 IEEE International Symposium on Industrial Electronics, IEEE-ISlE

Y2 - 4 May 2004 through 7 May 2004

ER -

Embedded processors optimization with hardware in the loop

Abstract

Conference

Keywords

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Cite this