Energy efficiency of SISO algorithms for turbo-decoding message-passing LDPC decoders

Erick Amador; Vincent Rezard; Renaud Pacalet

doi:10.1109/VLSISOC.2009.6041337

Energy efficiency of SISO algorithms for turbo-decoding message-passing LDPC decoders

Erick Amador
, Vincent Rezard
, Renaud Pacalet

Eurecom
Infineon Technologies France S.A.S

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

The decoding of LDPC codes using the turbo-decoding message-passing strategy is considered. This strategy can be used with different SISO message computation kernels. We analyze the suitability for VLSI implementation of various message computation algorithms in terms of implementation area, energy consumption and error-correcting performance. As one of the computation kernels, we introduce the recent Self-Corrected Min-Sum algorithm and show the advantages it brings from an energy efficiency perspective. We present comparisons among the studied kernels implemented in a 65nm CMOS process and use a test case from the codes defined in IEEE 802.11n to show differences in energy efficiency.

Original language	English
Title of host publication	Proceedings - 17th IFIP International Conference on Very Large Scale Integration, VLSI-SoC 2009
Publisher	IEEE Computer Society
Pages	95-100
Number of pages	6
ISBN (Print)	9781457702365
DOIs	https://doi.org/10.1109/VLSISOC.2009.6041337
Publication status	Published - 1 Jan 2009
Event	17th IFIP International Conference on Very Large Scale Integration, VLSI-SoC 2009 - Florianopolis, Brazil Duration: 12 Oct 2009 → 14 Oct 2009

Publication series

Name	Proceedings - 17th IFIP International Conference on Very Large Scale Integration, VLSI-SoC 2009

Conference

Conference	17th IFIP International Conference on Very Large Scale Integration, VLSI-SoC 2009
Country/Territory	Brazil
City	Florianopolis
Period	12/10/09 → 14/10/09

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

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10.1109/VLSISOC.2009.6041337

Cite this

Amador, E., Rezard, V., & Pacalet, R. (2009). Energy efficiency of SISO algorithms for turbo-decoding message-passing LDPC decoders. In Proceedings - 17th IFIP International Conference on Very Large Scale Integration, VLSI-SoC 2009 (pp. 95-100). Article 6041337 (Proceedings - 17th IFIP International Conference on Very Large Scale Integration, VLSI-SoC 2009). IEEE Computer Society. https://doi.org/10.1109/VLSISOC.2009.6041337

Amador, Erick ; Rezard, Vincent ; Pacalet, Renaud. / Energy efficiency of SISO algorithms for turbo-decoding message-passing LDPC decoders. Proceedings - 17th IFIP International Conference on Very Large Scale Integration, VLSI-SoC 2009. IEEE Computer Society, 2009. pp. 95-100 (Proceedings - 17th IFIP International Conference on Very Large Scale Integration, VLSI-SoC 2009).

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title = "Energy efficiency of SISO algorithms for turbo-decoding message-passing LDPC decoders",

abstract = "The decoding of LDPC codes using the turbo-decoding message-passing strategy is considered. This strategy can be used with different SISO message computation kernels. We analyze the suitability for VLSI implementation of various message computation algorithms in terms of implementation area, energy consumption and error-correcting performance. As one of the computation kernels, we introduce the recent Self-Corrected Min-Sum algorithm and show the advantages it brings from an energy efficiency perspective. We present comparisons among the studied kernels implemented in a 65nm CMOS process and use a test case from the codes defined in IEEE 802.11n to show differences in energy efficiency.",

author = "Erick Amador and Vincent Rezard and Renaud Pacalet",

year = "2009",

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day = "1",

doi = "10.1109/VLSISOC.2009.6041337",

language = "English",

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series = "Proceedings - 17th IFIP International Conference on Very Large Scale Integration, VLSI-SoC 2009",

publisher = "IEEE Computer Society",

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booktitle = "Proceedings - 17th IFIP International Conference on Very Large Scale Integration, VLSI-SoC 2009",

note = "17th IFIP International Conference on Very Large Scale Integration, VLSI-SoC 2009 ; Conference date: 12-10-2009 Through 14-10-2009",

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Amador, E, Rezard, V & Pacalet, R 2009, Energy efficiency of SISO algorithms for turbo-decoding message-passing LDPC decoders. in Proceedings - 17th IFIP International Conference on Very Large Scale Integration, VLSI-SoC 2009., 6041337, Proceedings - 17th IFIP International Conference on Very Large Scale Integration, VLSI-SoC 2009, IEEE Computer Society, pp. 95-100, 17th IFIP International Conference on Very Large Scale Integration, VLSI-SoC 2009, Florianopolis, Brazil, 12/10/09. https://doi.org/10.1109/VLSISOC.2009.6041337

Energy efficiency of SISO algorithms for turbo-decoding message-passing LDPC decoders. / Amador, Erick; Rezard, Vincent; Pacalet, Renaud.
Proceedings - 17th IFIP International Conference on Very Large Scale Integration, VLSI-SoC 2009. IEEE Computer Society, 2009. p. 95-100 6041337 (Proceedings - 17th IFIP International Conference on Very Large Scale Integration, VLSI-SoC 2009).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

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N2 - The decoding of LDPC codes using the turbo-decoding message-passing strategy is considered. This strategy can be used with different SISO message computation kernels. We analyze the suitability for VLSI implementation of various message computation algorithms in terms of implementation area, energy consumption and error-correcting performance. As one of the computation kernels, we introduce the recent Self-Corrected Min-Sum algorithm and show the advantages it brings from an energy efficiency perspective. We present comparisons among the studied kernels implemented in a 65nm CMOS process and use a test case from the codes defined in IEEE 802.11n to show differences in energy efficiency.

AB - The decoding of LDPC codes using the turbo-decoding message-passing strategy is considered. This strategy can be used with different SISO message computation kernels. We analyze the suitability for VLSI implementation of various message computation algorithms in terms of implementation area, energy consumption and error-correcting performance. As one of the computation kernels, we introduce the recent Self-Corrected Min-Sum algorithm and show the advantages it brings from an energy efficiency perspective. We present comparisons among the studied kernels implemented in a 65nm CMOS process and use a test case from the codes defined in IEEE 802.11n to show differences in energy efficiency.

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DO - 10.1109/VLSISOC.2009.6041337

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SN - 9781457702365

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BT - Proceedings - 17th IFIP International Conference on Very Large Scale Integration, VLSI-SoC 2009

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Amador E, Rezard V, Pacalet R. Energy efficiency of SISO algorithms for turbo-decoding message-passing LDPC decoders. In Proceedings - 17th IFIP International Conference on Very Large Scale Integration, VLSI-SoC 2009. IEEE Computer Society. 2009. p. 95-100. 6041337. (Proceedings - 17th IFIP International Conference on Very Large Scale Integration, VLSI-SoC 2009). doi: 10.1109/VLSISOC.2009.6041337

Energy efficiency of SISO algorithms for turbo-decoding message-passing LDPC decoders

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