TY - GEN
T1 - Ensuring safety and reliability of IP-based system design-A container approach
AU - Chandrasekharan, Arun
AU - Schmitz, Kenneth
AU - Kuhne, Ulrich
AU - Drechsler, Rolf
N1 - Publisher Copyright:
© 2015 IEEE.
PY - 2016/2/23
Y1 - 2016/2/23
N2 - The application of built-to-order embedded hardware designs in safety critical systems requires a high design quality and robustness during operation. Flawless execution of the involved software can be compromised by malfunctioning hardware components or by software-induced errors. Furthermore, intellectual property (IP) tends to become unavoidable in modern hardware designs. Any unexpected behavior of IP components may cause unrecoverable system errors. In order to construct correct and safe systems from unverified and potentially malicious components, we propose a system integration approach which encapsulates IP blocks in verifiable container modules. The synthesis of these container modules is driven by a domain specific language (DSL) augmented with sequential extended regular expressions (SEREs). The approach is demonstrated by showing the synthesis of an effective countermeasure against software-induced memory disturbance errors.
AB - The application of built-to-order embedded hardware designs in safety critical systems requires a high design quality and robustness during operation. Flawless execution of the involved software can be compromised by malfunctioning hardware components or by software-induced errors. Furthermore, intellectual property (IP) tends to become unavoidable in modern hardware designs. Any unexpected behavior of IP components may cause unrecoverable system errors. In order to construct correct and safe systems from unverified and potentially malicious components, we propose a system integration approach which encapsulates IP blocks in verifiable container modules. The synthesis of these container modules is driven by a domain specific language (DSL) augmented with sequential extended regular expressions (SEREs). The approach is demonstrated by showing the synthesis of an effective countermeasure against software-induced memory disturbance errors.
KW - Container-Verification
KW - Model-to-HDL Synthesis
KW - Safe IP Integration
KW - Safety
U2 - 10.1109/RSP.2015.7416550
DO - 10.1109/RSP.2015.7416550
M3 - Conference contribution
AN - SCOPUS:84963765796
T3 - Proceedings - IEEE International Symposium on Rapid System Prototyping, RSP
SP - 76
EP - 82
BT - Proceedings of the 2015 26th International Symposium on Rapid System Prototyping
PB - IEEE Computer Society
T2 - 26th International Symposium on Rapid System Prototyping, RSP 2015
Y2 - 8 October 2015 through 9 October 2015
ER -