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Estimation techniques for timing mismatch in time-interleaved analog-to-digital converters: Limitations and solutions

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Time interleaving (TI) is one of the best approaches to relax the speed-power trade-off of analog-to-digital converters (ADC). However, channel mismatches especially timing can limit the resolution of TIADC if they are not addressed properly. To achieve an efficient calibration for these errors, the most difficult task is the error estimation in the digital domain. The correction is less problematic and can be done either in digital domain or in the analog domain. Two big families of estimation techniques are commonly employed: the free-band estimation and the cross-correlation estimation. This paper reviews and analyses these estimation techniques and highlights their limitations. It also presents solutions to overcome these limitations.

Original languageEnglish
Title of host publication2016 IEEE International Conference on Electronics, Circuits and Systems, ICECS 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages297-300
Number of pages4
ISBN (Electronic)9781509061136
DOIs
Publication statusPublished - 1 Jan 2016
Externally publishedYes
Event23rd IEEE International Conference on Electronics, Circuits and Systems, ICECS 2016 - Monte Carlo, Monaco
Duration: 11 Dec 201614 Dec 2016

Publication series

Name2016 IEEE International Conference on Electronics, Circuits and Systems, ICECS 2016

Conference

Conference23rd IEEE International Conference on Electronics, Circuits and Systems, ICECS 2016
Country/TerritoryMonaco
CityMonte Carlo
Period11/12/1614/12/16

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