Evaluating CLB designs under multiple SETs in SRAM-based FPGAs

Arwa Ben Dhia; Lirida Naviner; Philippe Matherat

doi:10.1109/DFT.2013.6653592

Evaluating CLB designs under multiple SETs in SRAM-based FPGAs

Arwa Ben Dhia, Lirida Naviner, Philippe Matherat

CNRS LTCI

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

Defects as well as soft errors are a growing concern in micro and nanoelectronics. Multiple faults induced by single event effects are expected to be seen more often. Thus, reliability has become an important design criterion. In this context, we are concerned about the susceptibility of SRAM-based FPGA's logic blocks to multiple single event transients. Our target is to select the most reliable CLB design among different architectures of hardened CLBs, under the constraint of limited overheads. After synthesizing the candidate CLB architectures in STM 65nm CMOS technology, we compare them in terms of logical masking and reliability, and evaluate their area, time and power overheads. The most reliable CLB design is selected according to a metric expressing the tradeoff between the reliability gain and the cost penalties.

Original language	English
Title of host publication	Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2013
Pages	112-117
Number of pages	6
DOIs	https://doi.org/10.1109/DFT.2013.6653592
Publication status	Published - 1 Dec 2013
Externally published	Yes
Event	2013 26th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2013 - New York City, NY, United States Duration: 2 Oct 2013 → 4 Oct 2013

Publication series

Name	Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
ISSN (Print)	1550-5774

Conference

Conference	2013 26th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2013
Country/Territory	United States
City	New York City, NY
Period	2/10/13 → 4/10/13

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10.1109/DFT.2013.6653592

Cite this

Dhia, A. B., Naviner, L., & Matherat, P. (2013). Evaluating CLB designs under multiple SETs in SRAM-based FPGAs. In Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2013 (pp. 112-117). Article 6653592 (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems). https://doi.org/10.1109/DFT.2013.6653592

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title = "Evaluating CLB designs under multiple SETs in SRAM-based FPGAs",

abstract = "Defects as well as soft errors are a growing concern in micro and nanoelectronics. Multiple faults induced by single event effects are expected to be seen more often. Thus, reliability has become an important design criterion. In this context, we are concerned about the susceptibility of SRAM-based FPGA's logic blocks to multiple single event transients. Our target is to select the most reliable CLB design among different architectures of hardened CLBs, under the constraint of limited overheads. After synthesizing the candidate CLB architectures in STM 65nm CMOS technology, we compare them in terms of logical masking and reliability, and evaluate their area, time and power overheads. The most reliable CLB design is selected according to a metric expressing the tradeoff between the reliability gain and the cost penalties.",

author = "Dhia, \{Arwa Ben\} and Lirida Naviner and Philippe Matherat",

year = "2013",

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note = "2013 26th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2013 ; Conference date: 02-10-2013 Through 04-10-2013",

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Dhia, AB, Naviner, L & Matherat, P 2013, Evaluating CLB designs under multiple SETs in SRAM-based FPGAs. in Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2013., 6653592, Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 112-117, 2013 26th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2013, New York City, NY, United States, 2/10/13. https://doi.org/10.1109/DFT.2013.6653592

Evaluating CLB designs under multiple SETs in SRAM-based FPGAs. / Dhia, Arwa Ben; Naviner, Lirida; Matherat, Philippe.
Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2013. 2013. p. 112-117 6653592 (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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N2 - Defects as well as soft errors are a growing concern in micro and nanoelectronics. Multiple faults induced by single event effects are expected to be seen more often. Thus, reliability has become an important design criterion. In this context, we are concerned about the susceptibility of SRAM-based FPGA's logic blocks to multiple single event transients. Our target is to select the most reliable CLB design among different architectures of hardened CLBs, under the constraint of limited overheads. After synthesizing the candidate CLB architectures in STM 65nm CMOS technology, we compare them in terms of logical masking and reliability, and evaluate their area, time and power overheads. The most reliable CLB design is selected according to a metric expressing the tradeoff between the reliability gain and the cost penalties.

AB - Defects as well as soft errors are a growing concern in micro and nanoelectronics. Multiple faults induced by single event effects are expected to be seen more often. Thus, reliability has become an important design criterion. In this context, we are concerned about the susceptibility of SRAM-based FPGA's logic blocks to multiple single event transients. Our target is to select the most reliable CLB design among different architectures of hardened CLBs, under the constraint of limited overheads. After synthesizing the candidate CLB architectures in STM 65nm CMOS technology, we compare them in terms of logical masking and reliability, and evaluate their area, time and power overheads. The most reliable CLB design is selected according to a metric expressing the tradeoff between the reliability gain and the cost penalties.

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Dhia AB, Naviner L, Matherat P. Evaluating CLB designs under multiple SETs in SRAM-based FPGAs. In Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2013. 2013. p. 112-117. 6653592. (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems). doi: 10.1109/DFT.2013.6653592

Evaluating CLB designs under multiple SETs in SRAM-based FPGAs

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