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Evaluating KASLR Break on RISC-V Using Gem5: Microarchitectural Side-Channel Analysis of Page-Table Walks

  • Institut Polytechnique de Paris

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

This paper leverages the gem5 simulator to analyze a microarchitectural KASLR break on RISC-V systems. Previous research [2] demonstrated the feasibility of KASLR breaks on RISC-V hardware platforms (C906 and U74). Our paper aims to provide insights that are not easily attainable through traditional hardware experiments. By employing gem5, we gain access to fine-grained metrics such as cycle counts, cache behavior, branch prediction statistics, and TLB accesses, among others. These detailed insights give a deeper analysis of the KASLR bypass and help understand the attack mechanics better.

Original languageEnglish
Title of host publicationCybersecurity - 9th European Interdisciplinary Cybersecurity Conference, EICC 2025, Proceedings
EditorsIsabel Praça, Simona Bernardi, Pedro R.M. Inácio
PublisherSpringer Science and Business Media Deutschland GmbH
Pages229-235
Number of pages7
ISBN (Print)9783031948541
DOIs
Publication statusPublished - 1 Jan 2025
Event9th European Interdisciplinary Cybersecurity Conference, EICC 2025 - Rennes, France
Duration: 18 Jun 202519 Jun 2025

Publication series

NameCommunications in Computer and Information Science
Volume2500 CCIS
ISSN (Print)1865-0929
ISSN (Electronic)1865-0937

Conference

Conference9th European Interdisciplinary Cybersecurity Conference, EICC 2025
Country/TerritoryFrance
CityRennes
Period18/06/2519/06/25

Keywords

  • Cache Timing Analysis
  • Embedded Systems
  • Microarchitectural Security
  • Side-Channel Attacks
  • gem5 Simulator

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