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Evaluation of ASIPs design with LISATek

  • Telecom Paris

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

This paper evaluates an ASIP design methodology based on the extension of an existing instruction set and architecture described with LISA 2.0 language. The objective is to accelerate the ASIPs design process by using partially predefined, configurable RISC-like embedded processor cores that can be quickly tuned to given applications by means of ISE (Instruction Set Extension) techniques. A case study demonstrates the methodological approach for the JPEG algorithm.

Original languageEnglish
Title of host publicationEmbedded Computer Systems
Subtitle of host publicationArchitectures, Modeling, and Simulation - 8th International Workshop, SAMOS 2008, Proceedings
Pages177-186
Number of pages10
DOIs
Publication statusPublished - 5 Sept 2008
Event8th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS 2008 - Samos, Greece
Duration: 21 Jul 200824 Jul 2008

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume5114 LNCS
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349

Conference

Conference8th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS 2008
Country/TerritoryGreece
CitySamos
Period21/07/0824/07/08

Keywords

  • ASIPs
  • Customized instructions
  • JPEG
  • LISATek

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