Exploration of 2D EDA tool impact on the 3D MPSoC architectures performance

The need for higher performance devices to enable more complex applications continues to drive the growth of electronic design especially in the mobile markets. 3D integration is one of the feasible technologies to increase the system's performance and device integration by stacking multiple dies interconnected using through silicon vias (TSV). NoC-based Multiprocessor System on Chip (MPSoC) architecture has become the primary technology to provide higher performance to support more complex applications. In this paper, we perform an exploration and analysis of 2D EDA tool parameters impact on the 3D MPSoC architectures (3D Mesh MPSoC and heterogeneous 3D MPSoC stacking) performance in terms of timing and power characteristics. Exploration results show that the 2D EDA tool parameters have strong impact on the timing performance compared with power consumption. Furthermore, it is also shown that heterogeneous 3D MPSoC architecture has less footprint area, higher speed and less power consumption compared with 3D Mesh MPSoC for the same number of processing elements suggesting that it is a better design approach considering the limitation capability of 2D EDA tools for 3D design.