Fabrication and characterization of ion-doped p-type nanocrystalline silicon thin-film transistors

We report on the fabrication of coplanar p-channel nanocrystalline silicon thin-film transistors (nc-Si TFT) by using conventional boron ion doping, p-channel TFTs are necessary to implement complementary metal-oxide- semiconductor (CMOS) circuits with low power consumption, but amorphous silicon and polycrystalline silicon p-channel TFTs both have drawbacks, such as low hole mobility, high cost and poor uniformity. On the other hand, nanocrystalline silicon shows many merits, encouraging its use in CMOS circuits such as reasonable carrier mobility, high uniformity and ease of processing, despite these advantages, very few studies of p-type nanocrystalline silicon TFTs have been performed and there have been no documented efforts to adopt an ion-doped coplanar structure or to optimize its fabrication process. The TFTs presented herein have been fabricated using a conventional ion-doping process and show reasonably optimized characteristics, so the result demonstrated in this paper can be immediately adopted in a large-area, industrial system with little adjustment. Moreover, it is quite a new concept to use nanocrystalline silicon thin films for coplanar p-channel TFTs. The nanocrystalline silicon thin-films used in this work were grown on glass substrates at a low substrate temperature of 200 °C by using a SiF₄/H₂/Ar mixture. The TFTs that resulted from these films exhibited a field-effect mobility of 1.52 cm ²/Vs, a gate voltage swing of 1.1 V/dec, an on/off ratio in excess of 10⁶ and a threshold voltage of -6.28 V.