TY - GEN
T1 - FASE
T2 - 2006 IEEE International Conference on Reconfigurable Computing and FPGA's, ReConFig 2006
AU - Chaudhuri, Sumanta
AU - Danger, Jean Luc
AU - Guilley, Sylvain
AU - Hoogvorst, Philippe
PY - 2006/12/1
Y1 - 2006/12/1
N2 - The Run-Tune Reconfigurable (RTR) feature is highly desirable for flexible and fast self-contained systems. RTR can be achieved on some commercial FPGA platforms. We propose an open solution, called FASE, that allows for fine-grain RTR, designed to be more intuitive than currently available solutions. The issues of initializing RTR soft IP-cores and a design flow to manage the dynamics of RTR are presented. In the context of secure embedded systems, there is a need for both flexibility and tamper-resistance. However, the robustness level for security constraints is difficult to get and to prove because of the proprietary hidden structures. The EASE architecture addresses these issues. It makes it possible for any designer to implement custom and arbitraiy dynamic strategies. We illustrate two case studies: an implementation-level counter-measure against side-channel attacks and an efficient strategy to thwart fault injection attacks against ciyptographic functions.
AB - The Run-Tune Reconfigurable (RTR) feature is highly desirable for flexible and fast self-contained systems. RTR can be achieved on some commercial FPGA platforms. We propose an open solution, called FASE, that allows for fine-grain RTR, designed to be more intuitive than currently available solutions. The issues of initializing RTR soft IP-cores and a design flow to manage the dynamics of RTR are presented. In the context of secure embedded systems, there is a need for both flexibility and tamper-resistance. However, the robustness level for security constraints is difficult to get and to prove because of the proprietary hidden structures. The EASE architecture addresses these issues. It makes it possible for any designer to implement custom and arbitraiy dynamic strategies. We illustrate two case studies: an implementation-level counter-measure against side-channel attacks and an efficient strategy to thwart fault injection attacks against ciyptographic functions.
UR - https://www.scopus.com/pages/publications/46449123501
U2 - 10.1109/RECONF.2006.307752
DO - 10.1109/RECONF.2006.307752
M3 - Conference contribution
AN - SCOPUS:46449123501
SN - 1424406900
SN - 9781424406906
T3 - Proceedings of the 2006 IEEE International Conference on Reconfigurable Computing and FPGA's, ReConFig 2006
SP - 47
EP - 55
BT - Proceedings of the 2006 IEEE International Conference on Reconfigurable Computing and FPGA's, ReConFig 2006
Y2 - 20 September 2006 through 22 September 2006
ER -