Abstract
A flexible and reconfigurable receiver architecture for the WCDMA high data rate connections is presented. The proposed architecture consists of a single computational unit featuring the demodulation of one channel path and the suppression of one term of the inter-path interference with minimal configuration logic and routing. This unit is used in a serial fashion to perform the total channel demodulation and IPI suppression. It is controlled by the supervisor, an intelligent architectural element, in order to optimise system performance over a computational power constraint.
| Original language | English |
|---|---|
| Pages (from-to) | 22-24 |
| Number of pages | 3 |
| Journal | Electronics Letters |
| Volume | 41 |
| Issue number | 1 |
| DOIs | |
| Publication status | Published - 6 Jan 2005 |