@inproceedings{e9a82cabddf24dc7bf7ec0f43e687c02,
title = "FPGA design of an open-loop true random number generator",
abstract = "This paper presents the design methodology of a metastability-based True Random Number Generator (TRNG) on a Xilinx FPGA. As its structure is based on an open-loop delay chain, it provides both high throughput and security against physical attacks since it is not sensitive to coupling attacks as for oscillator-based TRNG. The proposed architecture, implemented in a Virtex-5 XC5VLX50T, uses 4\% of the available resources and generates random bits at a 20 Mbps rate. This work gives a detailed description of the design methodology, more specifically the placement, routing and timing analysis of the TRNG structure. Also, the randomness quality of this TRNG has been validated using AIS-31 and NIST statistical tests.",
keywords = "Delay chain, FPGA, LUT, Metastability, P\&R constraints, TRNG",
author = "Florent Lozac'h and Molka Ben-Romdhane and Tarik Graba and Danger, \{Jean Luc\}",
year = "2013",
month = dec,
day = "16",
doi = "10.1109/DSD.2013.73",
language = "English",
isbn = "9780769550749",
series = "Proceedings - 16th Euromicro Conference on Digital System Design, DSD 2013",
pages = "615--622",
booktitle = "Proceedings - 16th Euromicro Conference on Digital System Design, DSD 2013",
note = "16th Euromicro Conference on Digital System Design, DSD 2013 ; Conference date: 04-09-2013 Through 06-09-2013",
}