Fully parametrable downsampler generator

Lirida A.B. De Naviner; Jean François Naviner; Marcelo Alves De Barros

Fully parametrable downsampler generator

Lirida A.B. De Naviner
, Jean François Naviner
, Marcelo Alves De Barros

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

This paper deals with customized implementation of downsampling processors. We present an all-programmable generator of downsamplers to synthetise efficient decimator filters for many applications. This tool, written in VHDL language, is able to create cascade of generic FIR/CIC filters and helps fast exploration/evaluation of different hardware solutions for a given problem.

Original language	English
Title of host publication	Proceedings of the Fourth IEEE International Symposium on Signal Processing and Information Technology
Pages	503-506
Number of pages	4
Publication status	Published - 1 Dec 2004
Externally published	Yes
Event	Fourth IEEE International Symposium on Signal processing and Information Technology, ISSPIT 2004 - Rome, Italy Duration: 18 Dec 2004 → 21 Dec 2004

Publication series

Name	Proceedings of the Fourth IEEE International Symposium on Signal Processing and Information Technology, ISSPIT 2004

Conference

Conference	Fourth IEEE International Symposium on Signal processing and Information Technology, ISSPIT 2004
Country/Territory	Italy
City	Rome
Period	18/12/04 → 21/12/04

Keywords

Downsampling processors
Filtering
Hardware IP

Cite this

@inproceedings{9c6d93508fff47cab74ffa6128f2ebb2,

title = "Fully parametrable downsampler generator",

abstract = "This paper deals with customized implementation of downsampling processors. We present an all-programmable generator of downsamplers to synthetise efficient decimator filters for many applications. This tool, written in VHDL language, is able to create cascade of generic FIR/CIC filters and helps fast exploration/evaluation of different hardware solutions for a given problem.",

keywords = "Downsampling processors, Filtering, Hardware IP",

author = "\{De Naviner\}, \{Lirida A.B.\} and Naviner, \{Jean Fran{\c c}ois\} and \{De Barros\}, \{Marcelo Alves\}",

year = "2004",

month = dec,

day = "1",

language = "English",

isbn = "0780386892",

series = "Proceedings of the Fourth IEEE International Symposium on Signal Processing and Information Technology, ISSPIT 2004",

pages = "503--506",

booktitle = "Proceedings of the Fourth IEEE International Symposium on Signal Processing and Information Technology",

note = "Fourth IEEE International Symposium on Signal processing and Information Technology, ISSPIT 2004 ; Conference date: 18-12-2004 Through 21-12-2004",

}

De Naviner, LAB, Naviner, JF & De Barros, MA 2004, Fully parametrable downsampler generator. in Proceedings of the Fourth IEEE International Symposium on Signal Processing and Information Technology. Proceedings of the Fourth IEEE International Symposium on Signal Processing and Information Technology, ISSPIT 2004, pp. 503-506, Fourth IEEE International Symposium on Signal processing and Information Technology, ISSPIT 2004, Rome, Italy, 18/12/04.

Fully parametrable downsampler generator. / De Naviner, Lirida A.B.; Naviner, Jean François; De Barros, Marcelo Alves.
Proceedings of the Fourth IEEE International Symposium on Signal Processing and Information Technology. 2004. p. 503-506 (Proceedings of the Fourth IEEE International Symposium on Signal Processing and Information Technology, ISSPIT 2004).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Fully parametrable downsampler generator

AU - De Naviner, Lirida A.B.

AU - Naviner, Jean François

AU - De Barros, Marcelo Alves

PY - 2004/12/1

Y1 - 2004/12/1

N2 - This paper deals with customized implementation of downsampling processors. We present an all-programmable generator of downsamplers to synthetise efficient decimator filters for many applications. This tool, written in VHDL language, is able to create cascade of generic FIR/CIC filters and helps fast exploration/evaluation of different hardware solutions for a given problem.

AB - This paper deals with customized implementation of downsampling processors. We present an all-programmable generator of downsamplers to synthetise efficient decimator filters for many applications. This tool, written in VHDL language, is able to create cascade of generic FIR/CIC filters and helps fast exploration/evaluation of different hardware solutions for a given problem.

KW - Downsampling processors

KW - Filtering

KW - Hardware IP

UR - https://www.scopus.com/pages/publications/21544456678

M3 - Conference contribution

AN - SCOPUS:21544456678

SN - 0780386892

T3 - Proceedings of the Fourth IEEE International Symposium on Signal Processing and Information Technology, ISSPIT 2004

SP - 503

EP - 506

BT - Proceedings of the Fourth IEEE International Symposium on Signal Processing and Information Technology

T2 - Fourth IEEE International Symposium on Signal processing and Information Technology, ISSPIT 2004

Y2 - 18 December 2004 through 21 December 2004

ER -

Fully parametrable downsampler generator

Abstract

Publication series

Conference

Keywords

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Cite this