Graduate education to fight system level design productivity gap in SOC design

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Design productivity gap in System on Chip (SOC) design is the most severe challenge for continuous growth of the semiconductor industry. Considerable pressure is put on EDA research to come up with appropriate Electronic System Level (ESL) design methodologies in order to meet stringent time to market (TTM) constraints in this very cost sensitive industry. Multiple abstraction levels and platform based design methodologies have been the primary answers to this challenge. In this paper we describe our experience of a project oriented SOC graduate level course which combines the learning of multiple abstraction levels and platform based design to fight fixed amount of course time and time constrained learning curves to educate future engineers.

Original languageEnglish
Title of host publicationProceedings - MSE 2007
Subtitle of host publication2007 IEEE International Conference on Microelectronic Systems Education: Educating Systems Designers for the Global Economy and a Secure World
Pages45-46
Number of pages2
DOIs
Publication statusPublished - 25 Sept 2007
EventMSE 2007: 2007 IEEE International Conference on Microelectronic Systems Education: Educating Systems Designers for the Global Economy and a Secure World - San Diego, CA, United States
Duration: 3 Jun 20074 Jun 2007

Publication series

NameProceedings - MSE 2007: 2007 IEEE International Conference on Microelectronic Systems Education: Educating Systems Designers for the Global Economy and a Secure World

Conference

ConferenceMSE 2007: 2007 IEEE International Conference on Microelectronic Systems Education: Educating Systems Designers for the Global Economy and a Secure World
Country/TerritoryUnited States
CitySan Diego, CA
Period3/06/074/06/07

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