TY - GEN
T1 - High density Spin-Transfer Torque (STT)-MRAM based on cross-point architecture
AU - Zhao, Weisheng
AU - Chaudhuri, Sumanta
AU - Accoto, Celso
AU - Klein, Jacques Olivier
AU - Ravelosona, Dafiné
AU - Chappert, Claude
AU - Mazoyer, Pascale
PY - 2012/7/27
Y1 - 2012/7/27
N2 - Spin transfer torque magnetic random access memory (STT-MRAM) is considered as one of the most promising candidates to build up a true universal memory thanks to its fast write/read speed, infinite endurance and non-volatility. However the conventional access architecture based on 1 transistor + 1 memory cell limits its storage density as the selection transistor should be large enough to ensure the write current higher than the critical current for the STT operation. This paper describes a design of cross-point architecture for STT-MRAM. The mean area per word corresponds to only two transistors, which are shared by a number of bits (e.g. 64). This leads to significant improvement of data density (e.g. 1.75 F2/bit). Special techniques are also presented to address the sneak currents and low speed issues of conventional cross-point architecture.
AB - Spin transfer torque magnetic random access memory (STT-MRAM) is considered as one of the most promising candidates to build up a true universal memory thanks to its fast write/read speed, infinite endurance and non-volatility. However the conventional access architecture based on 1 transistor + 1 memory cell limits its storage density as the selection transistor should be large enough to ensure the write current higher than the critical current for the STT operation. This paper describes a design of cross-point architecture for STT-MRAM. The mean area per word corresponds to only two transistors, which are shared by a number of bits (e.g. 64). This leads to significant improvement of data density (e.g. 1.75 F2/bit). Special techniques are also presented to address the sneak currents and low speed issues of conventional cross-point architecture.
UR - https://www.scopus.com/pages/publications/84864144572
U2 - 10.1109/IMW.2012.6213618
DO - 10.1109/IMW.2012.6213618
M3 - Conference contribution
AN - SCOPUS:84864144572
SN - 9781467310802
T3 - 2012 4th IEEE International Memory Workshop, IMW 2012
BT - 2012 4th IEEE International Memory Workshop, IMW 2012
T2 - 2012 4th IEEE International Memory Workshop, IMW 2012
Y2 - 20 May 2012 through 23 May 2012
ER -