TY - JOUR
T1 - High-level modeling of communication-centric applications
T2 - Extensions to a system-level design and virtual prototyping tool
AU - Genius, Daniela
AU - Apvrille, Ludovic
AU - Li, Letitia W.
N1 - Publisher Copyright:
© 2019 Elsevier B.V.
PY - 2019/6/1
Y1 - 2019/6/1
N2 - High performance streaming applications require hardware platforms featuring complex, multi-level interconnects. These applications often resemble a task-farm, where many identical tasks listen to the same input channel. Usual embedded system design tools are not well adapted to capture these applications. In particular, the non-uniform memory access (NUMA) nature of the platforms induces latencies that must be carefully examined. The paper proposes a multi-level modeling methodology and tools (TTool, SoCLib) that have been extended to model the characteristics of streaming applications (multiple tasks, non deterministic behavior, I/O devices) in UML/SysML, and to automatically generate a virtual prototype that can be simulated with high precision. The paper uses a typical streaming application to show how latencies can be estimated and fed back to diagrams.
AB - High performance streaming applications require hardware platforms featuring complex, multi-level interconnects. These applications often resemble a task-farm, where many identical tasks listen to the same input channel. Usual embedded system design tools are not well adapted to capture these applications. In particular, the non-uniform memory access (NUMA) nature of the platforms induces latencies that must be carefully examined. The paper proposes a multi-level modeling methodology and tools (TTool, SoCLib) that have been extended to model the characteristics of streaming applications (multiple tasks, non deterministic behavior, I/O devices) in UML/SysML, and to automatically generate a virtual prototype that can be simulated with high precision. The paper uses a typical streaming application to show how latencies can be estimated and fed back to diagrams.
KW - Design space exploration
KW - System-level design
KW - Virtual prototyping
U2 - 10.1016/j.micpro.2019.03.006
DO - 10.1016/j.micpro.2019.03.006
M3 - Article
AN - SCOPUS:85063696104
SN - 0141-9331
VL - 67
SP - 117
EP - 130
JO - Microprocessors and Microsystems
JF - Microprocessors and Microsystems
ER -