High-level system modeling for rapid HW/SW architecture exploration

Chafic Jaber; Andreas Kanstein; Ludovic Apvrille; Amer Baghdadi; Patricia Le Moënner; Renaud Pacalet

doi:10.1109/RSP.2009.27

High-level system modeling for rapid HW/SW architecture exploration

Chafic Jaber
, Andreas Kanstein
, Ludovic Apvrille
, Amer Baghdadi
, Patricia Le Moënner
, Renaud Pacalet

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

The increasing complexity of system-on-chip design - especially the software part of those systems - has stimulated much research work on design space exploration at the early stages of system development. In this paper we propose a new methodology for system modeling based on a specific UML profile. It defines a high design abstraction level for modeling and analyzing hardware resource sharing between system elements. Additionally, a SystemC-based simulator is developed in order to simulate modeled systems and evaluate their performance. Due to the high level of abstraction, the developed simulator enables fast exploration of design solutions. First promising results are presented and discussed over a mobile platform for the 3GPP LTE protocol stack.

Original language	English
Title of host publication	Proceedings - 20th IEEE/IFIP International Symposium on Rapid System Prototyping
Subtitle of host publication	Shortening the Path from Specification to Prototype, RSP 2009
Pages	88-94
Number of pages	7
DOIs	https://doi.org/10.1109/RSP.2009.27
Publication status	Published - 9 Nov 2009
Event	20th IEEE/IFIP International Symposium on Rapid System Prototyping: Shortening the Path from Specification to Prototype, RSP 2009 - Paris, France Duration: 23 Jun 2009 → 26 Jun 2009

Publication series

Name	Proceedings of the International Workshop on Rapid System Prototyping
ISSN (Print)	1074-6005

Conference

Conference	20th IEEE/IFIP International Symposium on Rapid System Prototyping: Shortening the Path from Specification to Prototype, RSP 2009
Country/Territory	France
City	Paris
Period	23/06/09 → 26/06/09

Access to Document

10.1109/RSP.2009.27

Cite this

Jaber, C., Kanstein, A., Apvrille, L., Baghdadi, A., Le Moënner, P., & Pacalet, R. (2009). High-level system modeling for rapid HW/SW architecture exploration. In Proceedings - 20th IEEE/IFIP International Symposium on Rapid System Prototyping: Shortening the Path from Specification to Prototype, RSP 2009 (pp. 88-94). Article 5158504 (Proceedings of the International Workshop on Rapid System Prototyping). https://doi.org/10.1109/RSP.2009.27

@inproceedings{0942018a1eae4343b13b3306d949a31e,

title = "High-level system modeling for rapid HW/SW architecture exploration",

abstract = "The increasing complexity of system-on-chip design - especially the software part of those systems - has stimulated much research work on design space exploration at the early stages of system development. In this paper we propose a new methodology for system modeling based on a specific UML profile. It defines a high design abstraction level for modeling and analyzing hardware resource sharing between system elements. Additionally, a SystemC-based simulator is developed in order to simulate modeled systems and evaluate their performance. Due to the high level of abstraction, the developed simulator enables fast exploration of design solutions. First promising results are presented and discussed over a mobile platform for the 3GPP LTE protocol stack.",

author = "Chafic Jaber and Andreas Kanstein and Ludovic Apvrille and Amer Baghdadi and \{Le Mo{\"e}nner\}, Patricia and Renaud Pacalet",

year = "2009",

month = nov,

day = "9",

doi = "10.1109/RSP.2009.27",

language = "English",

isbn = "9780769536903",

series = "Proceedings of the International Workshop on Rapid System Prototyping",

pages = "88--94",

booktitle = "Proceedings - 20th IEEE/IFIP International Symposium on Rapid System Prototyping",

note = "20th IEEE/IFIP International Symposium on Rapid System Prototyping: Shortening the Path from Specification to Prototype, RSP 2009 ; Conference date: 23-06-2009 Through 26-06-2009",

}

Jaber, C, Kanstein, A, Apvrille, L, Baghdadi, A, Le Moënner, P & Pacalet, R 2009, High-level system modeling for rapid HW/SW architecture exploration. in Proceedings - 20th IEEE/IFIP International Symposium on Rapid System Prototyping: Shortening the Path from Specification to Prototype, RSP 2009., 5158504, Proceedings of the International Workshop on Rapid System Prototyping, pp. 88-94, 20th IEEE/IFIP International Symposium on Rapid System Prototyping: Shortening the Path from Specification to Prototype, RSP 2009, Paris, France, 23/06/09. https://doi.org/10.1109/RSP.2009.27

High-level system modeling for rapid HW/SW architecture exploration. / Jaber, Chafic; Kanstein, Andreas; Apvrille, Ludovic et al.
Proceedings - 20th IEEE/IFIP International Symposium on Rapid System Prototyping: Shortening the Path from Specification to Prototype, RSP 2009. 2009. p. 88-94 5158504 (Proceedings of the International Workshop on Rapid System Prototyping).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - High-level system modeling for rapid HW/SW architecture exploration

AU - Jaber, Chafic

AU - Kanstein, Andreas

AU - Apvrille, Ludovic

AU - Baghdadi, Amer

AU - Le Moënner, Patricia

AU - Pacalet, Renaud

PY - 2009/11/9

Y1 - 2009/11/9

N2 - The increasing complexity of system-on-chip design - especially the software part of those systems - has stimulated much research work on design space exploration at the early stages of system development. In this paper we propose a new methodology for system modeling based on a specific UML profile. It defines a high design abstraction level for modeling and analyzing hardware resource sharing between system elements. Additionally, a SystemC-based simulator is developed in order to simulate modeled systems and evaluate their performance. Due to the high level of abstraction, the developed simulator enables fast exploration of design solutions. First promising results are presented and discussed over a mobile platform for the 3GPP LTE protocol stack.

AB - The increasing complexity of system-on-chip design - especially the software part of those systems - has stimulated much research work on design space exploration at the early stages of system development. In this paper we propose a new methodology for system modeling based on a specific UML profile. It defines a high design abstraction level for modeling and analyzing hardware resource sharing between system elements. Additionally, a SystemC-based simulator is developed in order to simulate modeled systems and evaluate their performance. Due to the high level of abstraction, the developed simulator enables fast exploration of design solutions. First promising results are presented and discussed over a mobile platform for the 3GPP LTE protocol stack.

U2 - 10.1109/RSP.2009.27

DO - 10.1109/RSP.2009.27

M3 - Conference contribution

AN - SCOPUS:70350688177

SN - 9780769536903

T3 - Proceedings of the International Workshop on Rapid System Prototyping

SP - 88

EP - 94

BT - Proceedings - 20th IEEE/IFIP International Symposium on Rapid System Prototyping

T2 - 20th IEEE/IFIP International Symposium on Rapid System Prototyping: Shortening the Path from Specification to Prototype, RSP 2009

Y2 - 23 June 2009 through 26 June 2009

ER -

Jaber C, Kanstein A, Apvrille L, Baghdadi A, Le Moënner P, Pacalet R. High-level system modeling for rapid HW/SW architecture exploration. In Proceedings - 20th IEEE/IFIP International Symposium on Rapid System Prototyping: Shortening the Path from Specification to Prototype, RSP 2009. 2009. p. 88-94. 5158504. (Proceedings of the International Workshop on Rapid System Prototyping). doi: 10.1109/RSP.2009.27

High-level system modeling for rapid HW/SW architecture exploration

Abstract

Publication series

Conference

Access to Document

Fingerprint

Cite this