Linear programming based design of reconfigurable network on chip on eFPGA

Xinyu Li, Omar Hammami

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Multiprocessors system on chip are expected to be used for multiple applications which might exhibit distinct communication patterns. Finding a common efficient network on chip for these multiple applications might be simply impossible due to the diverging requirements. Reconfigurable network on chip is a potential solution in which the network is reconfigured before application execution in order to match the application specific requirements. Implementation of this reconfigurability might be done using eFPGA. In this paper we propose a methodology to specify the area dimension of reconfigurable eFPGA for NoC (Network on Chip). Various objective functions are used to drive out study. Experimental results show the effectiveness of our approach.

Original languageEnglish
Title of host publicationProceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008
Pages782-785
Number of pages4
DOIs
Publication statusPublished - 26 Dec 2008
Event15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008 - St. Julian's, Malta
Duration: 31 Aug 20083 Sept 2008

Publication series

NameProceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008

Conference

Conference15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008
Country/TerritoryMalta
CitySt. Julian's
Period31/08/083/09/08

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