Microarchitectural Analysis of Speculative Execution Patterns in RISC-V using Machine Learning and ISA-Level Masking Wrappers

Speculative execution attacks, such as Spectre Variant 1, leak sensitive data through transient microarchitectural effects. This paper presents a machine learning-based framework for analyzing and mitigating speculative execution vulnerability patterns in RISC-V systems. We extract branch, cache, and timing features from gem5 simulations and validate leakage behavior on a SiFive HiFive Premier P550 platform. Supervised models achieve up to 97.1% accuracy in distinguishing benign and speculative-leak execution windows, while unsupervised methods (K-means, HDBSCAN, and Isolation Forest) independently reveal structural and anomaly-based separation. Feature analysis shows that speculative loads and memory latency are the strongest leakage indicators. We further propose lightweight RISC-V assembly wrappers based on index masking and fence instructions. Results demonstrate that these wrappers shift vulnerable execution toward benign microarchitectural behavior. The proposed approach combines simulation, hardware validation, and learning-based analysis for practical speculative vulnerability analysis and mitigation in RISC-V processors.