Minimum operating voltage due to intrinsic noise in subthreshold digital logic in nanoscale CMOS

Intrinsic noise has been predicted as a limit to CMOS scaling. If this is the case, the effect would be more severe at low supply voltages, such as the ones applied in subthreshold digital circuits. In this work we analysed the effect of intrinsic noise in subthreshold digital nanoscale CMOS for the first time. We took into consideration key issues such as variability and the actual bandwidth of the studied circuits. Most of previous works overestimate the impact of intrinsic noise due to the use of simplified models of the MOS transistor. We used BSIM4 transistor model and PTM model files in order to correctly calculate noise RMS voltage at the output node of an inverter, which has not been done before in the subthreshold region. Using this analysis we search for the minimum operating voltage due to intrinsic noise. We also explored how technology scaling impacts this minimum operating voltage by simulating technology nodes from 130 nm down to 16 nm and considering variability down to 28 nm. Simulation results show that minimum operating voltage of subthreshold CMOS digital circuits strongly increases due to variability effects and due to the increased intrinsic noise in gates implemented with smaller transistors in advanced technologies. This makes that minimum energy operation might not be achieved in advanced technologies due to intrinsic noise.