@inproceedings{4536c65518ae42399a5ee463a39b84b9,
title = "Model-Driven Engineering for Designing Safe and Secure Embedded Systems",
abstract = "The communication capabilities of recent embedded systems offer more opportunities for attack tocyber criminals. Moreover, those attacks may compromisethe safety of these systems. SysML-Sec is a SysML-basedenvironment for the design of such embedded systems withsafety and security features. The paper focuses on the SysML-Sec methodology containing the following stages: assumptions, requirements, attacks, partitioning, software design and software deployment. Ourmethod is supported by TTool, and offers a press-buttonapproach for formal proof of safety and security. Previousprojects and case studies modeled and validated with SysML-Sec range from automotive systems, drone systems, information systems (e.g., the analysis of malware targeting bankingsystems), industrial systems (Analysis of SCADA malware), and more generally, security protocols.",
keywords = "Model-driven engineering, SysML, UML, formal description technique, formal proof, model checking, safety, security, software engineering",
author = "Ludovic Apvrille and Letitia Li and Yves Roudier",
note = "Publisher Copyright: {\textcopyright} 2016 IEEE.; 3rd Architecture-Centric Virtual Integration, ACVI 2016 ; Conference date: 05-04-2016",
year = "2016",
month = jul,
day = "12",
doi = "10.1109/ACVI.2016.6",
language = "English",
series = "Proceedings - 2016 Architecture-Centric Virtual Integration, ACVI 2016",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "4--7",
booktitle = "Proceedings - 2016 Architecture-Centric Virtual Integration, ACVI 2016",
}