@inproceedings{13aadf6b17494e5cb433cc31f051a507,
title = "Modeling of transient faults and fault-tolerant design in nanoelectronics",
abstract = "Transistors in nanometric technologies are increasingly susceptible to faults due to physical limitations. Since the constituent gates of a logic circuit actually have different failure rates, the assumption of constant gate failure rate in existing reliability evaluation and fault tolerant design is not desirable. This paper analyzes transient faults in CMOS logic gates at transistor level and proposes a mathematical model. Examples based on the benchmark circuit are provided to demonstrate the efficiency of the proposed model in both reliability evaluation and fault tolerant design.",
author = "Tian Ban and Jianxin Wang and Ting An and Lirida Naviner",
year = "2013",
month = dec,
day = "1",
doi = "10.1109/MWSCAS.2013.6674706",
language = "English",
isbn = "9781479900664",
series = "Midwest Symposium on Circuits and Systems",
pages = "545--548",
booktitle = "2013 IEEE 56th International Midwest Symposium on Circuits and Systems, MWSCAS 2013",
note = "2013 IEEE 56th International Midwest Symposium on Circuits and Systems, MWSCAS 2013 ; Conference date: 04-08-2013 Through 07-08-2013",
}