@inproceedings{62bc3d336bec41a581ec2c822a0f3e1c,
title = "MRAM-on-FDSOI Integration: A bit-cell perspective",
abstract = "In this paper we discuss the potential foundry announced hybrid integration of magnetic random access memory (MRAM) on fully depleted silicon-on-insulator (FD-SOI) technology. The spin transfer torque magnetic tunnel junction (STT-MTJ) and the next generation voltage-controlled magnetic anisotropy (VCMA) MTJ are separately integrated into a 28 nm FD-SOI process. Circuit-level design strategies are explored that use FD-SOI leverage and spin-device characteristic to realize writing and reading power-delay efficiency, robust and reliable performance in a 1-Transistor 1-MTJ (1T1M) bit cell. Process variation aware strategies for MTJ-FDSOI integration are proposed to compensate failure operations, by using the dynamic step-wise back-bias and the flip-well back-bias. A qualitative summary demonstrates that the MRAM-on-FDSOI integration offers attractive performance for future non-volatile CMOS integration.",
keywords = "Bit cell, FDSOI, MRAM, STT MTJ, VCMA MTJ",
author = "Hao Cai and You Wang and Wang Kang and Lirida Naviner and Xinning Liu and Jun Yang and Weisheng Zhao",
note = "Publisher Copyright: {\textcopyright} 2018 IEEE.; 17th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2018 ; Conference date: 09-07-2018 Through 11-07-2018",
year = "2018",
month = aug,
day = "7",
doi = "10.1109/ISVLSI.2018.00056",
language = "English",
isbn = "9781538670996",
series = "Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI",
publisher = "IEEE Computer Society",
pages = "263--268",
booktitle = "Proceedings - 2018 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2018",
}