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Multi-FPGA emulation of a 48-Cores multiprocessor with NOC

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Design productivity is one the most important challenge facing future generation multiprocessor system on chip (MPSOC). The modeling of dozens of interconnected IPs with distributed memories implies intensive manual EDA based design activity. We propose to improve design productivity by raising IP reuse to small scale multiprocessor IP combined with fast extension techniques for system level design automation in the framework of multi-FPGA based emulator. A design case study of a 48-processors multiprocessor on 4 large scale FPGA based industry class emulator validates our approach.

Original languageEnglish
Title of host publicationProceediangs - 2008 3rd International Design and Test Workshop, IDT 2008
Pages205-208
Number of pages4
DOIs
Publication statusPublished - 1 Dec 2008
Event2008 3rd International Design and Test Workshop, IDT 2008 - Monastir, Tunisia
Duration: 20 Dec 200822 Dec 2008

Publication series

NameProceedings - 2008 3rd International Design and Test Workshop, IDT 2008

Conference

Conference2008 3rd International Design and Test Workshop, IDT 2008
Country/TerritoryTunisia
CityMonastir
Period20/12/0822/12/08

Keywords

  • Emulation
  • MPSOC
  • Multi-FPGA
  • NoC

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