Multi-level latency evaluation with an MDE approach

Daniela Genius, Letitia W. Li, Ludovic Apvrille, Tullio Tanzi

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Designing embedded systems includes two main phases: (i) HW/SW Partitioning performed from high-level functional and architecture models, and (ii) Software Design performed with significantly more detailed models. Partitioning decisions are made according to performance assumptions that should be validated on the more refined software models. In this paper, we focus on one such metric: latencies between operations. We show how they can be modeled at different abstraction levels (partitioning, SW design) and how they can help determine accuracy of the computational complexity estimates made during HW/SW Partitioning.

Original languageEnglish
Title of host publicationMODELSWARD 2018 - Proceedings of the 6th International Conference on Model-Driven Engineering and Software Development
EditorsSlimane Hammoudi, Luis Ferreira Pires, Bran Selic
PublisherSciTePress
Pages295-302
Number of pages8
ISBN (Electronic)9789897582837
DOIs
Publication statusPublished - 1 Jan 2018
Externally publishedYes
Event6th International Conference on Model-Driven Engineering and Software Development, MODELSWARD 2018 - Funchal, Madeira, Portugal
Duration: 22 Jan 201824 Jan 2018

Publication series

NameMODELSWARD 2018 - Proceedings of the 6th International Conference on Model-Driven Engineering and Software Development
Volume2018-January

Conference

Conference6th International Conference on Model-Driven Engineering and Software Development, MODELSWARD 2018
Country/TerritoryPortugal
CityFunchal, Madeira
Period22/01/1824/01/18

Keywords

  • Embedded Systems
  • Latency
  • Simulation
  • System-level Design
  • Virtual Prototyping

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