Multi-objective Network-on-Chip synthesis with transaction level simulation

Xinyu Li; Omar Hammami

doi:10.1109/ICM.2010.5696195

Multi-objective Network-on-Chip synthesis with transaction level simulation

Xinyu Li
, Omar Hammami

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

The Network-on-Chip (NoC) synthesis problem consists in generating NoC topology to guarantee system design objectives such as: system performance and area. A novel multi-objective NoC synthesis solver is proposed to design application specific NoC of multi-stage topology. Based on NSGAII, a multi-objective genetic algorithm, the solver aims to supply multi-objective Pareto solutions set for the multiple design objectives rather than one single objective subset, so that designers can make flexible decisions according to different design objectives and budgets. The switch area model is obtained from RTL implementation and system performances are measured using SystemC TLM simulation. Experiments on multimedia and general benchmark applications demonstrate the efficiency of this method.

Original language	English
Title of host publication	2010 International Conference on Microelectronics, ICM'10
Pages	487-490
Number of pages	4
DOIs	https://doi.org/10.1109/ICM.2010.5696195
Publication status	Published - 1 Dec 2010
Event	2010 International Conference on Microelectronics, ICM'10 - Cairo, Egypt Duration: 19 Dec 2010 → 22 Dec 2010

Publication series

Name	Proceedings of the International Conference on Microelectronics, ICM

Conference

Conference	2010 International Conference on Microelectronics, ICM'10
Country/Territory	Egypt
City	Cairo
Period	19/12/10 → 22/12/10

Keywords

Multi-objective
NoC Synthesis
SystemC
TLM

Access to Document

10.1109/ICM.2010.5696195

Cite this

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title = "Multi-objective Network-on-Chip synthesis with transaction level simulation",

abstract = "The Network-on-Chip (NoC) synthesis problem consists in generating NoC topology to guarantee system design objectives such as: system performance and area. A novel multi-objective NoC synthesis solver is proposed to design application specific NoC of multi-stage topology. Based on NSGAII, a multi-objective genetic algorithm, the solver aims to supply multi-objective Pareto solutions set for the multiple design objectives rather than one single objective subset, so that designers can make flexible decisions according to different design objectives and budgets. The switch area model is obtained from RTL implementation and system performances are measured using SystemC TLM simulation. Experiments on multimedia and general benchmark applications demonstrate the efficiency of this method.",

keywords = "Multi-objective, NoC Synthesis, SystemC, TLM",

author = "Xinyu Li and Omar Hammami",

year = "2010",

month = dec,

day = "1",

doi = "10.1109/ICM.2010.5696195",

language = "English",

isbn = "9781612841519",

series = "Proceedings of the International Conference on Microelectronics, ICM",

pages = "487--490",

booktitle = "2010 International Conference on Microelectronics, ICM'10",

note = "2010 International Conference on Microelectronics, ICM'10 ; Conference date: 19-12-2010 Through 22-12-2010",

}

Li, X & Hammami, O 2010, Multi-objective Network-on-Chip synthesis with transaction level simulation. in 2010 International Conference on Microelectronics, ICM'10., 5696195, Proceedings of the International Conference on Microelectronics, ICM, pp. 487-490, 2010 International Conference on Microelectronics, ICM'10, Cairo, Egypt, 19/12/10. https://doi.org/10.1109/ICM.2010.5696195

TY - GEN

T1 - Multi-objective Network-on-Chip synthesis with transaction level simulation

AU - Li, Xinyu

AU - Hammami, Omar

PY - 2010/12/1

Y1 - 2010/12/1

N2 - The Network-on-Chip (NoC) synthesis problem consists in generating NoC topology to guarantee system design objectives such as: system performance and area. A novel multi-objective NoC synthesis solver is proposed to design application specific NoC of multi-stage topology. Based on NSGAII, a multi-objective genetic algorithm, the solver aims to supply multi-objective Pareto solutions set for the multiple design objectives rather than one single objective subset, so that designers can make flexible decisions according to different design objectives and budgets. The switch area model is obtained from RTL implementation and system performances are measured using SystemC TLM simulation. Experiments on multimedia and general benchmark applications demonstrate the efficiency of this method.

AB - The Network-on-Chip (NoC) synthesis problem consists in generating NoC topology to guarantee system design objectives such as: system performance and area. A novel multi-objective NoC synthesis solver is proposed to design application specific NoC of multi-stage topology. Based on NSGAII, a multi-objective genetic algorithm, the solver aims to supply multi-objective Pareto solutions set for the multiple design objectives rather than one single objective subset, so that designers can make flexible decisions according to different design objectives and budgets. The switch area model is obtained from RTL implementation and system performances are measured using SystemC TLM simulation. Experiments on multimedia and general benchmark applications demonstrate the efficiency of this method.

KW - Multi-objective

KW - NoC Synthesis

KW - SystemC

KW - TLM

UR - https://www.scopus.com/pages/publications/79951719951

U2 - 10.1109/ICM.2010.5696195

DO - 10.1109/ICM.2010.5696195

M3 - Conference contribution

AN - SCOPUS:79951719951

SN - 9781612841519

T3 - Proceedings of the International Conference on Microelectronics, ICM

SP - 487

EP - 490

BT - 2010 International Conference on Microelectronics, ICM'10

T2 - 2010 International Conference on Microelectronics, ICM'10

Y2 - 19 December 2010 through 22 December 2010

ER -

Multi-objective Network-on-Chip synthesis with transaction level simulation

Abstract

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Conference

Keywords

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