Multi-objective topology synthesis and FPGA prototyping framework of application specific network-on-chip

Network-on-Chip (NoC) topology synthesis problem targets to generate NoC topology for multiple system design objectives such as performance and area. A multi-objective NoC synthesis and prototyping framework based on FPGA platform is proposed to design application specific NoC. Using the multi-objective algorithm NSGAII, the workflow aims to supply Pareto solutions for the multiple design objectives, rather than one single objective subset, so that designers can make flexible decisions according to different design objectives and budgets. This multi-objective NoC synthesis is ensured by our complete TLM and RTL levels design framework. All the routers in the NoC library are synthesized for RTL implementation, and the area utilization information is used for hardware resource estimation at the high level NoC synthesis step. The system performances are obtained by SystemC TLM simulation with traffic defined in the core graph. After the high level NoC synthesis, the final selected Pareto solutions are generated and prototyped on FPGA platform with RTL traffic generators with same configurations as TLM level. Our multi-objective framework aims to provide a bridge from high level model to FPGA execution for accurate NoC design. Experiments on multimedia benchmark applications demonstrate the efficiency of this method.