NOC based MPSOC directory based cache coherency with OCP-IP protocol

Omar Hammami, Xinyu Li

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Rapid advances of silicon and parallel processing technologies allow the building of multiprocessor systems-on-chip (MPSoCs). Cache coherency problem becomes one of the major design issues to improve the performance of multiprocessor. We first realize a directory based cache coherency scheme of Network on Chip (NoC) based MPSOC implemented on FPGA using the industrial standard protocol of OCP-IP. In this paper we present the system architecture and implementation results which shows that NoC based coherency system is well scalable. JTAG and PCI based debug system are developed for visualizing the application execution of our NoC based MPSoC cache coherency system.

Original languageEnglish
Title of host publication2013 8th IEEE Design and Test Symposium, IDT 2013
DOIs
Publication statusPublished - 1 Dec 2013
Event2013 8th IEEE Design and Test Symposium, IDT 2013 - Marrakesh, Morocco
Duration: 16 Dec 201318 Dec 2013

Publication series

Name2013 8th IEEE Design and Test Symposium, IDT 2013

Conference

Conference2013 8th IEEE Design and Test Symposium, IDT 2013
Country/TerritoryMorocco
CityMarrakesh
Period16/12/1318/12/13

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