NOC monitoring feedback for parallel programmers

Large scale SOC designs require efficient scalable communication between IPs. Network-on-chip (NOC) provide such potential however with an increased complexity due to the large number of parameters to be tuned. Resulting efficient network-on-chip designs are of interest for both system architects and parallel programmers. Indeed, it is increasingly complex for parallel programmers to efficiently program large scale NOC-based SOC designs without adequate quick detailed non cumulative performance monitoring feedback. Although NOC monitoring can be conducted at simulation level it is too slow even at SystemC TLM level for large scale NOC-based designs with significant parallel software applications. In this paper we propose an emulation based fast Network-on-Chip monitoring methodology where specific Programmable monitors IPs are included in the design to provide the designer with instantaneous and actual performance results allowing him to improve both his architecture and his parallel software. A case study demonstrates the validity of our approach on a 2×2 NOC based SOC implemented on FPGA performing image processing.