NOC synthesis vs ITRS predictions: The challenges of linear programming based synthesis

Network on chip are fundamental in the performance of complex system on chip. Numerous solutions have been proposed both for regular and irregular topologies. Irregular or custom topologies present numerous benefits with regard to area/performance optimizations and can be automatically generated through NOC synthesis flows. NOC synthesis generates NOC topologies from application requirements coregraphs. NOC synthesis techniques use either exact or heuristic techniques. So far NOC synthesis techniques have not been benchmarked against ITRS roadmaps. We propose in this paper to benchmark linear programming based NOC synthesis techniques using NOCBENCH v.1.0 benchmarks. The results show that new models and techniques are needed to overcome complexity of future manycore.