@inproceedings{380b2b29e2bf4b5d99a8016c62b9f9bf,
title = "NOCEVE: Network on chip emulation and verification environment",
abstract = "We present in this paper NOCEVE an industrial Network on Chip (NoC) emulation and verification environment on industrial large scale multi-FPGA emulation platform for billion cycle application. It helps designer to improve system performance by the analysis of traffic distribution and balance through the network on chip. The hardware monitoring network is generated by another commercial NoC design tool. It consists of traffic collectors, which is reconfigurable to collect different traffic information such as packet latency and throughput. The statistic traffic information is collected during real application execution on FPGA platform and it is sent through monitoring network on FPGA and then PCI bright board back to host computer for real-time visualization or post-execution data analysis. NOCEVE is the first industrial NoC emulation and verification environment for billion cycle applications.",
keywords = "FPGA, NoC, emulation, verification",
author = "Omar Hammami and Xinyu Li and Brault, \{Jean Marc\}",
year = "2012",
month = jan,
day = "1",
doi = "10.1109/date.2012.6176452",
language = "English",
isbn = "9783981080186",
series = "Proceedings -Design, Automation and Test in Europe, DATE",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "163--164",
booktitle = "Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 2012",
note = "15th Design, Automation and Test in Europe Conference and Exhibition, DATE 2012 ; Conference date: 12-03-2012 Through 16-03-2012",
}