Novel architecture for high-pass cascaded Δ∑ modulator

High-pass (HP) delta-sigma (Δ∑) modulators find utilisation in applications which are sensitive to low-frequency noises because of their complete immunity to these noises (Nguyen in High-pass DS modulator and its application to time-interleaved DS converter, Ecole Nationale Supérieur des télécommunications, PhD Dissertation, 2004). Single-stage HP Δ∑ modulator of order-2 has been presented in Nguyen et al. (Proceedings of ISCAS, 2006). This paper presents a novel approach for HP cascaded Δ∑ modulator, which attains better dynamic range, stability and achievable SNR than conventional cascade architecture. This approach has the flexibility of using any second-order HP Δ∑ modulator architecture in the first stage. We have used traditional HP Δ∑ modulator (Nguyen et al. in Proceedings of ISCAS, 2006) and the HP version of Silva structure (Silva et al. in Electron Lett 37(12):737-738, 2001) which has the additional advantages of reduced sensitivity to switch and op-amp nonlinearities and reduced op-amp voltage swings requirement as first stages of this new cascade technique. The first-stage made up of Silva-based feedforward HP structure proves to be a better choice because of its insensitivity to op-amp non-idealities. The method of designing cascade consists of approximating quantizer-gain by functional simulation of the modulator and then keeping this value in view while designing digital filters. Digital filters designed this way are more efficient in cancelling quantization error and provide better results. System level simulations have been performed in Matlab and transistor level simulations have been carried out in SPECTRE, both of which prove the efficacity of our approach.