Novel Pulsed-Latch Replacement in Non-Volatile Flip-Flop Core

Hao Cai; You Wang; Lirida Naviner; Weisheng Zhao

doi:10.1109/ISVLSI.2017.19

Novel Pulsed-Latch Replacement in Non-Volatile Flip-Flop Core

Hao Cai
, You Wang
, Lirida Naviner
, Weisheng Zhao

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

In this paper, we propose efficient scalable nonvolatile flip-flops (NV-FF) with single-stage pulsed latch which is explored as the flip-flop core in hybrid CMOS/MTJ (magnetic tunnel junction) integration. Typical full-custom FF cores are implemented with a 28nm ultra-thin body and buried oxide (UTBB) fully depleted silicon-on-insulator (FD-SOI) technology. The performance analysis takes into account sensing delay, dynamic power, leakage power and process variations. Results show that the transmission gate pulsed latch (TGPL) based NVFF exhibits enhanced performance compared to conventional master-slave structure, with improved variability, 15.7% fast timing metric, 76% dynamic, 79% leakage power reduction and 30% layout area reduction in multi-bit NV-FF hybrid circuit integration. The pulsed latch FF core can enhance NVFF scalability with increased energy-delay and layout efficiency, as well as reduced active and leakage energy.

Original language	English
Title of host publication	Proceedings - 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017
Editors	Ricardo Reis, Mircea Stan, Michael Huebner, Nikolaos Voros
Publisher	IEEE Computer Society
Pages	57-61
Number of pages	5
ISBN (Electronic)	9781509067626
DOIs	https://doi.org/10.1109/ISVLSI.2017.19
Publication status	Published - 20 Jul 2017
Externally published	Yes
Event	2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017 - Bochum, North Rhine-Westfalia, Germany Duration: 3 Jul 2017 → 5 Jul 2017

Publication series

Name	Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI
Volume	2017-July
ISSN (Print)	2159-3469
ISSN (Electronic)	2159-3477

Conference

Conference	2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017
Country/Territory	Germany
City	Bochum, North Rhine-Westfalia
Period	3/07/17 → 5/07/17

Keywords

FDSOI
leakage reduction
low power
magnetic tunnel junction
non-volatile flip-flops

Access to Document

10.1109/ISVLSI.2017.19

Cite this

Cai, H., Wang, Y., Naviner, L., & Zhao, W. (2017). Novel Pulsed-Latch Replacement in Non-Volatile Flip-Flop Core. In R. Reis, M. Stan, M. Huebner, & N. Voros (Eds.), Proceedings - 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017 (pp. 57-61). Article 7987495 (Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI; Vol. 2017-July). IEEE Computer Society. https://doi.org/10.1109/ISVLSI.2017.19

Cai, Hao ; Wang, You ; Naviner, Lirida et al. / Novel Pulsed-Latch Replacement in Non-Volatile Flip-Flop Core. Proceedings - 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017. editor / Ricardo Reis ; Mircea Stan ; Michael Huebner ; Nikolaos Voros. IEEE Computer Society, 2017. pp. 57-61 (Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI).

@inproceedings{f6ad2c6f0cbc4e8185547c0ee500c542,

title = "Novel Pulsed-Latch Replacement in Non-Volatile Flip-Flop Core",

abstract = "In this paper, we propose efficient scalable nonvolatile flip-flops (NV-FF) with single-stage pulsed latch which is explored as the flip-flop core in hybrid CMOS/MTJ (magnetic tunnel junction) integration. Typical full-custom FF cores are implemented with a 28nm ultra-thin body and buried oxide (UTBB) fully depleted silicon-on-insulator (FD-SOI) technology. The performance analysis takes into account sensing delay, dynamic power, leakage power and process variations. Results show that the transmission gate pulsed latch (TGPL) based NVFF exhibits enhanced performance compared to conventional master-slave structure, with improved variability, 15.7\% fast timing metric, 76\% dynamic, 79\% leakage power reduction and 30\% layout area reduction in multi-bit NV-FF hybrid circuit integration. The pulsed latch FF core can enhance NVFF scalability with increased energy-delay and layout efficiency, as well as reduced active and leakage energy.",

keywords = "FDSOI, leakage reduction, low power, magnetic tunnel junction, non-volatile flip-flops",

author = "Hao Cai and You Wang and Lirida Naviner and Weisheng Zhao",

note = "Publisher Copyright: {\textcopyright} 2017 IEEE.; 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017 ; Conference date: 03-07-2017 Through 05-07-2017",

year = "2017",

month = jul,

day = "20",

doi = "10.1109/ISVLSI.2017.19",

language = "English",

series = "Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI",

publisher = "IEEE Computer Society",

pages = "57--61",

editor = "Ricardo Reis and Mircea Stan and Michael Huebner and Nikolaos Voros",

booktitle = "Proceedings - 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017",

}

Cai, H, Wang, Y, Naviner, L & Zhao, W 2017, Novel Pulsed-Latch Replacement in Non-Volatile Flip-Flop Core. in R Reis, M Stan, M Huebner & N Voros (eds), Proceedings - 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017., 7987495, Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI, vol. 2017-July, IEEE Computer Society, pp. 57-61, 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017, Bochum, North Rhine-Westfalia, Germany, 3/07/17. https://doi.org/10.1109/ISVLSI.2017.19

Novel Pulsed-Latch Replacement in Non-Volatile Flip-Flop Core. / Cai, Hao; Wang, You; Naviner, Lirida et al.
Proceedings - 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017. ed. / Ricardo Reis; Mircea Stan; Michael Huebner; Nikolaos Voros. IEEE Computer Society, 2017. p. 57-61 7987495 (Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI; Vol. 2017-July).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Novel Pulsed-Latch Replacement in Non-Volatile Flip-Flop Core

AU - Cai, Hao

AU - Wang, You

AU - Naviner, Lirida

AU - Zhao, Weisheng

PY - 2017/7/20

Y1 - 2017/7/20

N2 - In this paper, we propose efficient scalable nonvolatile flip-flops (NV-FF) with single-stage pulsed latch which is explored as the flip-flop core in hybrid CMOS/MTJ (magnetic tunnel junction) integration. Typical full-custom FF cores are implemented with a 28nm ultra-thin body and buried oxide (UTBB) fully depleted silicon-on-insulator (FD-SOI) technology. The performance analysis takes into account sensing delay, dynamic power, leakage power and process variations. Results show that the transmission gate pulsed latch (TGPL) based NVFF exhibits enhanced performance compared to conventional master-slave structure, with improved variability, 15.7% fast timing metric, 76% dynamic, 79% leakage power reduction and 30% layout area reduction in multi-bit NV-FF hybrid circuit integration. The pulsed latch FF core can enhance NVFF scalability with increased energy-delay and layout efficiency, as well as reduced active and leakage energy.

AB - In this paper, we propose efficient scalable nonvolatile flip-flops (NV-FF) with single-stage pulsed latch which is explored as the flip-flop core in hybrid CMOS/MTJ (magnetic tunnel junction) integration. Typical full-custom FF cores are implemented with a 28nm ultra-thin body and buried oxide (UTBB) fully depleted silicon-on-insulator (FD-SOI) technology. The performance analysis takes into account sensing delay, dynamic power, leakage power and process variations. Results show that the transmission gate pulsed latch (TGPL) based NVFF exhibits enhanced performance compared to conventional master-slave structure, with improved variability, 15.7% fast timing metric, 76% dynamic, 79% leakage power reduction and 30% layout area reduction in multi-bit NV-FF hybrid circuit integration. The pulsed latch FF core can enhance NVFF scalability with increased energy-delay and layout efficiency, as well as reduced active and leakage energy.

KW - FDSOI

KW - leakage reduction

KW - low power

KW - magnetic tunnel junction

KW - non-volatile flip-flops

U2 - 10.1109/ISVLSI.2017.19

DO - 10.1109/ISVLSI.2017.19

M3 - Conference contribution

AN - SCOPUS:85027254262

T3 - Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI

SP - 57

EP - 61

BT - Proceedings - 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017

A2 - Reis, Ricardo

A2 - Stan, Mircea

A2 - Huebner, Michael

A2 - Voros, Nikolaos

PB - IEEE Computer Society

T2 - 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017

Y2 - 3 July 2017 through 5 July 2017

ER -

Cai H, Wang Y, Naviner L, Zhao W. Novel Pulsed-Latch Replacement in Non-Volatile Flip-Flop Core. In Reis R, Stan M, Huebner M, Voros N, editors, Proceedings - 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017. IEEE Computer Society. 2017. p. 57-61. 7987495. (Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI). doi: 10.1109/ISVLSI.2017.19

Novel Pulsed-Latch Replacement in Non-Volatile Flip-Flop Core

Abstract

Publication series

Conference

Keywords

Access to Document

Fingerprint

Cite this