Novel Self-Timing Speculative Writing for Unreliable STT-MRAM

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Considering the insatiable demand for emerging embedded non-volatile memory (NVM), spin-Transfer torque magnetic random access memory (STT-MRAM) can be configured with high access speed, readily hybrid integration and guaranteed endurance/retention, which becomes one of the most promising candidates among different types of NVM. However, the major drawback of STT-MRAM is that high switching energy is required, accompanied with unreliable writing operation. In this work, we propose a speculative MRAM writing scheme using self-Timing implementation, including speculative/ deterministic write operation and a judgment mechanism. Simulation results show that the speculative scheme can achieve 40% less writing power consumption and 50% less latency during write operation compared to standard writing method. The bit-error rate (BER) is maintained at 10-9 without inevitable cost.

Original languageEnglish
Title of host publication2020 IEEE 15th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2020 - Proceedings
EditorsShaofeng Yu, Xiaona Zhu, Ting-Ao Tang
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728162355
DOIs
Publication statusPublished - 3 Nov 2020
Event15th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2020 - Virtual, Kunming, China
Duration: 3 Nov 20206 Nov 2020

Publication series

Name2020 IEEE 15th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2020 - Proceedings

Conference

Conference15th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2020
Country/TerritoryChina
CityVirtual, Kunming
Period3/11/206/11/20

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