On evaluating the signal reliability of self-checking arithmetic circuits

Fault-tolerant design approaches have been studied as a possible solution for the expected reduction in the reliability of nanoscale integrated circuits. The increase in functional reliability, obtained with fault-tolerant design techniques, comes at a price, i.e., hardware or temporal redundancy. The resulting overhead can be justified in mission critical applications but for consumer electronics, one of the drivers of nanoscale circuits, other criteria, e.g., signal reliability and time penalty, must be considered when evaluating the use of fault-tolerant designs. To study the impact of fault-tolerant designs in the behavior of combinational circuits, some fault- tolerant adders were evaluated, based on the Probabilistic Binomial Reliability model, targeting signal reliability and time penalty. The results obtained show the compromises associated with redundant designs.