On-the-fly syndrome check for LDPC decoders

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Abstract

Modern VLSI decoders for low-density parity-check (LDPC) codes require high throughput performance while achieving high energy efficiency on the smallest possible footprint. In this paper we present a valuable optimization to the processing step known as syndrome check. After each decoding iteration the updated posterior values are used to verify the validity of the codeblock and halt the decoding task. We partition this task and perform it on-the-fly in order to speed up the total task latency and eliminate hardware components. We present results for applying this technique to an LDPC decoder for the IEEE 802.11n standard.

Original languageEnglish
Title of host publicationProceedings - 6th International Conference on Wireless and Mobile Communications, ICWMC 2010
Pages33-37
Number of pages5
DOIs
Publication statusPublished - 1 Dec 2010
Event6th International Conference on Wireless and Mobile Communications, ICWMC 2010 - Valencia, Spain
Duration: 20 Sept 201025 Sept 2010

Publication series

NameProceedings - 6th International Conference on Wireless and Mobile Communications, ICWMC 2010

Conference

Conference6th International Conference on Wireless and Mobile Communications, ICWMC 2010
Country/TerritorySpain
CityValencia
Period20/09/1025/09/10

Keywords

  • Iterative decoding
  • LDPC codes
  • Syndrome calculation
  • Throughput enhancement

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