On the output events in concurrent error detection schemes

Maí C.R. De Vasconcelos; Denis T. Franco; Lirida A.B. De Naviner; Jean François Naviner

doi:10.1109/ICECS.2008.4675019

On the output events in concurrent error detection schemes

Maí C.R. De Vasconcelos
, Denis T. Franco
, Lirida A.B. De Naviner
, Jean François Naviner

CNRS LTCI

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

Extra circuitry for concurrent error detection (CED) schemes is becoming an essential feature as IC technologies continue to scale. Soft errors have emerged as an important challenge in the nanoscale design and several works are dedicated to quantify the CED effective enhancement in systems dependability, but none of them makes a comprehensive description of the output events that can occur in such schemes. In this paper we propose a methodology to evaluate circuits with CED, including the time penalty as a relevant metric even in hardware redundancy techniques. We have also proposed a FPGA-based emulation platform to improve run-time performance.

Original language	English
Title of host publication	Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008
Pages	978-981
Number of pages	4
DOIs	https://doi.org/10.1109/ICECS.2008.4675019
Publication status	Published - 26 Dec 2008
Externally published	Yes
Event	15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008 - St. Julian's, Malta Duration: 31 Aug 2008 → 3 Sept 2008

Publication series

Name	Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008

Conference

Conference	15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008
Country/Territory	Malta
City	St. Julian's
Period	31/08/08 → 3/09/08

Keywords

Concurrent error detection
Fault tolerance
Reliability analysis
Self-checking operators
Soft errors

Access to Document

10.1109/ICECS.2008.4675019

Cite this

De Vasconcelos, M. C. R., Franco, D. T., De Naviner, L. A. B., & Naviner, J. F. (2008). On the output events in concurrent error detection schemes. In Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008 (pp. 978-981). Article 4675019 (Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008). https://doi.org/10.1109/ICECS.2008.4675019

@inproceedings{a521c52839e84f79b7158fbbe3c19bc4,

title = "On the output events in concurrent error detection schemes",

abstract = "Extra circuitry for concurrent error detection (CED) schemes is becoming an essential feature as IC technologies continue to scale. Soft errors have emerged as an important challenge in the nanoscale design and several works are dedicated to quantify the CED effective enhancement in systems dependability, but none of them makes a comprehensive description of the output events that can occur in such schemes. In this paper we propose a methodology to evaluate circuits with CED, including the time penalty as a relevant metric even in hardware redundancy techniques. We have also proposed a FPGA-based emulation platform to improve run-time performance.",

keywords = "Concurrent error detection, Fault tolerance, Reliability analysis, Self-checking operators, Soft errors",

author = "\{De Vasconcelos\}, \{Ma{\'i} C.R.\} and Franco, \{Denis T.\} and \{De Naviner\}, \{Lirida A.B.\} and Naviner, \{Jean Fran{\c c}ois\}",

year = "2008",

month = dec,

day = "26",

doi = "10.1109/ICECS.2008.4675019",

language = "English",

isbn = "9781424421824",

series = "Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008",

pages = "978--981",

booktitle = "Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008",

note = "15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008 ; Conference date: 31-08-2008 Through 03-09-2008",

}

De Vasconcelos, MCR, Franco, DT, De Naviner, LAB & Naviner, JF 2008, On the output events in concurrent error detection schemes. in Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008., 4675019, Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008, pp. 978-981, 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008, St. Julian's, Malta, 31/08/08. https://doi.org/10.1109/ICECS.2008.4675019

On the output events in concurrent error detection schemes. / De Vasconcelos, Maí C.R.; Franco, Denis T.; De Naviner, Lirida A.B. et al.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008. 2008. p. 978-981 4675019 (Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - On the output events in concurrent error detection schemes

AU - De Vasconcelos, Maí C.R.

AU - Franco, Denis T.

AU - De Naviner, Lirida A.B.

AU - Naviner, Jean François

PY - 2008/12/26

Y1 - 2008/12/26

N2 - Extra circuitry for concurrent error detection (CED) schemes is becoming an essential feature as IC technologies continue to scale. Soft errors have emerged as an important challenge in the nanoscale design and several works are dedicated to quantify the CED effective enhancement in systems dependability, but none of them makes a comprehensive description of the output events that can occur in such schemes. In this paper we propose a methodology to evaluate circuits with CED, including the time penalty as a relevant metric even in hardware redundancy techniques. We have also proposed a FPGA-based emulation platform to improve run-time performance.

AB - Extra circuitry for concurrent error detection (CED) schemes is becoming an essential feature as IC technologies continue to scale. Soft errors have emerged as an important challenge in the nanoscale design and several works are dedicated to quantify the CED effective enhancement in systems dependability, but none of them makes a comprehensive description of the output events that can occur in such schemes. In this paper we propose a methodology to evaluate circuits with CED, including the time penalty as a relevant metric even in hardware redundancy techniques. We have also proposed a FPGA-based emulation platform to improve run-time performance.

KW - Concurrent error detection

KW - Fault tolerance

KW - Reliability analysis

KW - Self-checking operators

KW - Soft errors

UR - https://www.scopus.com/pages/publications/57849122194

U2 - 10.1109/ICECS.2008.4675019

DO - 10.1109/ICECS.2008.4675019

M3 - Conference contribution

AN - SCOPUS:57849122194

SN - 9781424421824

T3 - Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008

SP - 978

EP - 981

BT - Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008

T2 - 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008

Y2 - 31 August 2008 through 3 September 2008

ER -

De Vasconcelos MCR, Franco DT, De Naviner LAB, Naviner JF. On the output events in concurrent error detection schemes. In Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008. 2008. p. 978-981. 4675019. (Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008). doi: 10.1109/ICECS.2008.4675019

On the output events in concurrent error detection schemes

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