Optimized FPGA-based Implementation of down-sampling filter for wide band radio receiver

Khaled Grati; Adel Ghazel; Lirida Naviner

Optimized FPGA-based Implementation of down-sampling filter for wide band radio receiver

Khaled Grati
, Adel Ghazel
, Lirida Naviner

Research output: Contribution to conference › Paper › peer-review

Abstract

To increase both the integration and adaptability to multiple RF communication standards, channel selection need to be performed on chip at base-band. This paper presents a low-power design and an area-efficient FPGA implementation of digital filtering cascade structure to meet multistandard radio communication specifications for a wide-band RF receiver. A filtering cascade composed of a 5^th order Comb filter, a half-band filter and a FIR selector filter is proposed. Design flow of hardware architecture is presented through digital data format representation and topology of digital operators definitions. Some experimental results are given to evaluate designed FPGA-based decimating filter circuit.

Original language	English
Pages	243-245
Number of pages	3
Publication status	Published - 1 Dec 2004
Event	2004 IEEE International Conference on Industrial Technology, ICIT - Hammamet, Tunisia Duration: 8 Dec 2004 → 10 Dec 2004

Conference

Conference	2004 IEEE International Conference on Industrial Technology, ICIT
Country/Territory	Tunisia
City	Hammamet
Period	8/12/04 → 10/12/04

Keywords

Digital decimating filter
FPGA implementation
Low-power design
Multistandard transceiver
Radio communications

Cite this

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title = "Optimized FPGA-based Implementation of down-sampling filter for wide band radio receiver",

abstract = "To increase both the integration and adaptability to multiple RF communication standards, channel selection need to be performed on chip at base-band. This paper presents a low-power design and an area-efficient FPGA implementation of digital filtering cascade structure to meet multistandard radio communication specifications for a wide-band RF receiver. A filtering cascade composed of a 5th order Comb filter, a half-band filter and a FIR selector filter is proposed. Design flow of hardware architecture is presented through digital data format representation and topology of digital operators definitions. Some experimental results are given to evaluate designed FPGA-based decimating filter circuit.",

keywords = "Digital decimating filter, FPGA implementation, Low-power design, Multistandard transceiver, Radio communications",

author = "Khaled Grati and Adel Ghazel and Lirida Naviner",

year = "2004",

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language = "English",

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TY - CONF

T1 - Optimized FPGA-based Implementation of down-sampling filter for wide band radio receiver

AU - Grati, Khaled

AU - Ghazel, Adel

AU - Naviner, Lirida

PY - 2004/12/1

Y1 - 2004/12/1

N2 - To increase both the integration and adaptability to multiple RF communication standards, channel selection need to be performed on chip at base-band. This paper presents a low-power design and an area-efficient FPGA implementation of digital filtering cascade structure to meet multistandard radio communication specifications for a wide-band RF receiver. A filtering cascade composed of a 5th order Comb filter, a half-band filter and a FIR selector filter is proposed. Design flow of hardware architecture is presented through digital data format representation and topology of digital operators definitions. Some experimental results are given to evaluate designed FPGA-based decimating filter circuit.

AB - To increase both the integration and adaptability to multiple RF communication standards, channel selection need to be performed on chip at base-band. This paper presents a low-power design and an area-efficient FPGA implementation of digital filtering cascade structure to meet multistandard radio communication specifications for a wide-band RF receiver. A filtering cascade composed of a 5th order Comb filter, a half-band filter and a FIR selector filter is proposed. Design flow of hardware architecture is presented through digital data format representation and topology of digital operators definitions. Some experimental results are given to evaluate designed FPGA-based decimating filter circuit.

KW - Digital decimating filter

KW - FPGA implementation

KW - Low-power design

KW - Multistandard transceiver

KW - Radio communications

M3 - Paper

AN - SCOPUS:27944489443

SP - 243

EP - 245

T2 - 2004 IEEE International Conference on Industrial Technology, ICIT

Y2 - 8 December 2004 through 10 December 2004

ER -

Optimized FPGA-based Implementation of down-sampling filter for wide band radio receiver

Abstract

Conference

Keywords

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